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Commit 33d919bd authored by PC Liao's avatar PC Liao Committed by Mark Brown
Browse files

ASoC: mediatek: Change the order of MCLK clock configuration 



Because MCLK opens later and closes earlier than codec, this patch
changes the order of MCLK clock configuration.

Signed-off-by: default avatarPC Liao <pc.liao@mediatek.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 1a695a90

sound/soc/mediatek/mtk-afe-pcm.c

+12 −4
Original line number Original line Diff line number Diff line
@@ -361,8 +361,6 @@ static int mtk_afe_i2s_startup(struct snd_pcm_substream *substream, 
	if (dai->active)

	if (dai->active)

		return 0;

		return 0;





	mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);

	mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S2_M], NULL);

	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,

	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,

			   AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0);

			   AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0);

	return 0;

	return 0;
@@ -381,8 +379,6 @@ static void mtk_afe_i2s_shutdown(struct snd_pcm_substream *substream, 
	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,

	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,

			   AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M,

			   AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M,

			   AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M);

			   AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M);

	mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);

	mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S2_M], NULL);

}

}





static int mtk_afe_i2s_prepare(struct snd_pcm_substream *substream,

static int mtk_afe_i2s_prepare(struct snd_pcm_substream *substream,
@@ -1134,6 +1130,8 @@ static int mtk_afe_runtime_suspend(struct device *dev) 
	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,

	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,

			   AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE);

			   AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE);





	clk_disable_unprepare(afe->clocks[MTK_CLK_I2S1_M]);

	clk_disable_unprepare(afe->clocks[MTK_CLK_I2S2_M]);

	clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]);

	clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]);

	clk_disable_unprepare(afe->clocks[MTK_CLK_BCK1]);

	clk_disable_unprepare(afe->clocks[MTK_CLK_BCK1]);

	clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD]);

	clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
@@ -1166,6 +1164,12 @@ static int mtk_afe_runtime_resume(struct device *dev) 
	ret = clk_prepare_enable(afe->clocks[MTK_CLK_BCK1]);

	ret = clk_prepare_enable(afe->clocks[MTK_CLK_BCK1]);

	if (ret)

	if (ret)

		goto err_bck0;

		goto err_bck0;

	ret = clk_prepare_enable(afe->clocks[MTK_CLK_I2S1_M]);

	if (ret)

		goto err_i2s1_m;

	ret = clk_prepare_enable(afe->clocks[MTK_CLK_I2S2_M]);

	if (ret)

		goto err_i2s2_m;





	/* enable AFE clk */

	/* enable AFE clk */

	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0);

	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0);
@@ -1181,6 +1185,10 @@ static int mtk_afe_runtime_resume(struct device *dev) 
	regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);

	regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);

	return 0;

	return 0;





err_i2s1_m:

	clk_disable_unprepare(afe->clocks[MTK_CLK_I2S1_M]);

err_i2s2_m:

	clk_disable_unprepare(afe->clocks[MTK_CLK_I2S2_M]);

err_bck0:

err_bck0:

	clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]);

	clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]);

err_top_aud:

err_top_aud: