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Commit 33696cdb authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: add display support for monaco IDP"

parents d028a56a f40d17f5

display/dsi-panel-rm69090-amoled-178-cmd.dtsi

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&mdss_mdp {

	dsi_rm69090_amoled_cmd: qcom,mdss_dsi_rm69090_amoled_178_cmd {

		qcom,mdss-dsi-panel-name =

			"RM69090 1.78 amoled cmd mode";

		qcom,mdss-dsi-panel-type = "dsi_cmd_mode";

		qcom,mdss-dsi-panel-physical-type = "oled";

		qcom,mdss-dsi-virtual-channel-id = <0>;

		qcom,mdss-dsi-stream = <0>;

		qcom,mdss-dsi-bpp = <24>;

		qcom,mdss-dsi-color-order = "rgb_swap_rgb";

		qcom,mdss-dsi-underflow-color = <0xff>;

		qcom,mdss-dsi-border-color = <0>;



		qcom,dsi-ctrl-num = <0>;

		qcom,dsi-phy-num = <0>;



		qcom,mdss-dsi-traffic-mode = "burst_mode";

		qcom,mdss-dsi-lane-map = "lane_map_0123";

		qcom,mdss-dsi-bllp-eof-power-mode;

		qcom,mdss-dsi-bllp-power-mode;

		qcom,mdss-dsi-lane-0-state;

		qcom,mdss-dsi-dma-trigger = "trigger_sw";

		qcom,mdss-dsi-mdp-trigger = "none";

		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;

		qcom,mdss-dsi-te-pin-select = <1>;

		qcom,mdss-dsi-te-dcs-command = <1>;

		qcom,mdss-dsi-te-check-enable;

		qcom,mdss-dsi-te-using-te-pin;

		qcom,mdss-dsi-t-clk-post = <0x09>;

		qcom,mdss-dsi-t-clk-pre = <0x2c>;



		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";

		qcom,mdss-dsi-bl-min-level = <1>;

		qcom,mdss-dsi-bl-max-level = <255>;



		qcom,mdss-dsi-display-timings {

			timing@0 {

				qcom,mdss-dsi-panel-framerate = <60>;

				qcom,mdss-dsi-panel-width = <368>;

				qcom,mdss-dsi-panel-height = <448>;

				qcom,mdss-dsi-h-front-porch = <40>;

				qcom,mdss-dsi-h-back-porch = <20>;

				qcom,mdss-dsi-h-pulse-width = <4>;

				qcom,mdss-dsi-h-sync-skew = <0>;

				qcom,mdss-dsi-v-back-porch = <8>;

				qcom,mdss-dsi-v-front-porch = <6>;

				qcom,mdss-dsi-v-pulse-width = <2>;

				qcom,mdss-dsi-h-left-border = <0>;

				qcom,mdss-dsi-h-right-border = <0>;

				qcom,mdss-dsi-v-top-border = <0>;

				qcom,mdss-dsi-v-bottom-border = <0>;



				qcom,mdss-dsi-on-command = [

					15 01 00 00 00 00 02 FE 01

					15 01 00 00 00 00 02 6A 03

					15 01 00 00 00 00 02 FE 00

					15 01 00 00 00 00 02 35 00

					15 01 00 00 00 00 02 51 FF

					39 01 00 00 00 00 05 2A 00 10 01 7F

					39 01 00 00 00 00 05 2B 00 00 01 BF

					05 01 00 00 78 00 02 11 00

					05 01 00 00 40 00 02 29 00

				];



				qcom,mdss-dsi-off-command = [

					05 01 00 00 14 00 02 28 00

					05 01 00 00 78 00 02 10 00

					15 01 00 00 00 00 02 4F 01];

				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";

				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";

			};

		};

	};

};

display/monaco-sde-display.dtsi

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#include <dt-bindings/clock/mdss-5nm-pll-clk.h>

#include "dsi-panel-rm69090-amoled-178-cmd.dtsi"



&soc {

	dsi_panel_pwr_supply: dsi_panel_pwr_supply {

		#address-cells = <1>;

		#size-cells = <0>;



		qcom,panel-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "vddio";

			qcom,supply-min-voltage = <1800000>;

			qcom,supply-max-voltage = <2000000>;

			qcom,supply-enable-load = <62000>;

			qcom,supply-disable-load = <80>;

			qcom,supply-post-on-sleep = <20>;

		};



		qcom,panel-supply-entry@1 {

			reg = <1>;

			qcom,supply-name = "lab";

			qcom,supply-min-voltage = <4600000>;

			qcom,supply-max-voltage = <6000000>;

			qcom,supply-enable-load = <100000>;

			qcom,supply-disable-load = <100>;

		};



		qcom,panel-supply-entry@2 {

			reg = <2>;

			qcom,supply-name = "ibb";

			qcom,supply-min-voltage = <4600000>;

			qcom,supply-max-voltage = <6000000>;

			qcom,supply-enable-load = <100000>;

			qcom,supply-disable-load = <100>;

			qcom,supply-post-on-sleep = <20>;

		};

	};



	dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {

		#address-cells = <1>;

		#size-cells = <0>;



		qcom,panel-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "vddio";

			qcom,supply-min-voltage = <1800000>;

			qcom,supply-max-voltage = <2000000>;

			qcom,supply-enable-load = <62000>;

			qcom,supply-disable-load = <80>;

			qcom,supply-post-on-sleep = <20>;

		};

	};



	dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled {

		#address-cells = <1>;

		#size-cells = <0>;



		qcom,panel-supply-entry@0 {

			reg = <0>;

			qcom,supply-name = "vddio";

			qcom,supply-min-voltage = <1800000>;

			qcom,supply-max-voltage = <2000000>;

			qcom,supply-enable-load = <62000>;

			qcom,supply-disable-load = <80>;

			qcom,supply-post-on-sleep = <20>;

		};



		qcom,panel-supply-entry@1 {

			reg = <1>;

			qcom,supply-name = "vdda-3p3";

			qcom,supply-min-voltage = <3000000>;

			qcom,supply-max-voltage = <3000000>;

			qcom,supply-enable-load = <13200>;

			qcom,supply-disable-load = <80>;

		};

	};



	sde_dsi: qcom,dsi-display-primary {

		compatible = "qcom,dsi-display";

		label = "primary";

		qcom,dsi-ctrl = <&mdss_dsi0>;

		qcom,dsi-phy = <&mdss_dsi_phy0>;



		clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,

			 <&mdss_dsi_phy0 PCLK_MUX_0_CLK>,

			 <&mdss_dsi_phy0 CPHY_BYTECLK_SRC_0_CLK>,

			 <&mdss_dsi_phy0 CPHY_PCLK_SRC_0_CLK>,

			 <&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>,

			 <&mdss_dsi_phy0 PCLK_SRC_0_CLK>,

			 <&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>,

			 <&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>,

			 <&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>,

			 <&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>;

		/*TODO: check if MDP clock WA is required*/

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

			"cphy_byte_clk0", "cphy_pixel_clk0",

			"src_byte_clk0", "src_pixel_clk0",

			"shadow_byte_clk0", "shadow_pixel_clk0",

			"shadow_cphybyte_clk0", "shadow_cphypixel_clk0";

		pinctrl-names = "panel_active", "panel_suspend";

		pinctrl-0 = <&sde_dsi_active &sde_te_active>;

		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;



		qcom,platform-te-gpio = <&tlmm 73 0>;

		qcom,panel-te-source = <0>;

		vddio-supply = <&L21A>;

		qcom,mdp = <&mdss_mdp>;



		qcom,dsi-default-panel =

			<&dsi_rm69090_amoled_cmd>;

	};

};



&mdss_mdp {

	  connectors = <&smmu_sde_unsec &sde_dsi>;

};



&dsi_rm69090_amoled_cmd {

	qcom,mdss-dsi-t-clk-post = <0x08>;

	qcom,mdss-dsi-t-clk-pre = <0x0B>;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", /*TODO: check these*/

				"src_byte_clk0", "src_pixel_clk0",

				"shadow_byte_clk0", "shadow_pixel_clk0";



	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 0C 03 03 10 1D 03

				03 03 02 02 04 0B 08];

			qcom,display-topology = <1 0 1>;

			qcom,default-topology-index = <0>;

		};

	};

};

display/monaco-sde.dtsi

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#include <dt-bindings/clock/mdss-5nm-pll-clk.h>



&soc {



	smmu_sde_unsec: qcom,smmu_sde_unsec_cb {

		compatible = "qcom,smmu_sde_unsec";

		iommus = <&apps_smmu 0x420 0x2>;

		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;

		qcom,iommu-faults = "non-fatal";

		qcom,iommu-earlymap; /* for cont-splash */

	};



	smmu_sde_sec: qcom,smmu_sde_sec_cb {

		compatible = "qcom,smmu_sde_sec";

		iommus = <&apps_smmu 0x421 0x0>;

		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;

		qcom,iommu-faults = "non-fatal";

		qcom,iommu-vmid = <0xa>;

	};





	mdss_mdp: qcom,mdss_mdp {

		compatible = "qcom,sde-kms";

		reg = <0x5e00000 0x8f030>,

		      <0x5eb0000 0x2008>,

		      <0x5e8f000 0x02c>,

		      <0xc125ba4 0x20>;

		reg-names = "mdp_phys",

			   "vbif_phys",

			   "sid_phys",

			   "sde_imem_phys";



		clocks =

			<&gcc GCC_DISP_AHB_CLK>,

			<&gcc GCC_DISP_HF_AXI_CLK>,

			<&gcc GCC_DISP_THROTTLE_CORE_CLK>,

			<&dispcc DISP_CC_MDSS_AHB_CLK>,

			<&dispcc DISP_CC_MDSS_MDP_CLK>,

			<&dispcc DISP_CC_MDSS_VSYNC_CLK>,

			<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;

		clock-names = "gcc_iface", "gcc_bus", "throttle_clk",

				"iface_clk", "core_clk", "vsync_clk",

				"lut_clk";

		clock-rate = <0 0 0 0 0 256000000 19200000 192000000>;

		clock-max-rate = <0 0 0 0 0 384000000 19200000 384000000>;



		sde-vdd-supply = <&mdss_core_gdsc>;



		/* data and reg bus scale settings */

		interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,

				<&bimc MASTER_AMPSS_M0

					&config_noc SLAVE_DISPLAY_CFG>;

		interconnect-names = "qcom,sde-data-bus0",

					"qcom,sde-reg-bus";



		/* interrupt config */

		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-controller;

		#interrupt-cells = <1>;



		#power-domain-cells = <0>;



		/* hw blocks */

		qcom,sde-off = <0x1000>;

		qcom,sde-len = <0x494>;



		qcom,sde-ctl-off = <0x2000>;

		qcom,sde-ctl-size = <0x1dc>;

		qcom,sde-ctl-display-pref = "primary";



		qcom,sde-mixer-off = <0x45000>;

		qcom,sde-mixer-size = <0x320>;

		qcom,sde-mixer-display-pref = "primary";



		qcom,sde-dspp-top-off = <0x1300>;

		qcom,sde-dspp-top-size = <0x80>;

		qcom,sde-dspp-off = <0x55000>;

		qcom,sde-dspp-size = <0xfe4>;



		qcom,sde-intf-off = <0x0 0x6b800>;

		qcom,sde-intf-size = <0x2b8>;

		qcom,sde-intf-type = "none", "dsi";



		qcom,sde-pp-off = <0x71000>;

		qcom,sde-pp-size = <0xd4>;



		qcom,sde-dither-off = <0x30e0>;

		qcom,sde-dither-version = <0x00010000>;

		qcom,sde-dither-size = <0x20>;



		qcom,sde-sspp-type = "vig", "dma";



		qcom,sde-sspp-off = <0x5000 0x25000>;

		qcom,sde-sspp-src-size = <0x1f8>;



		qcom,sde-sspp-xin-id = <0 1>;

		qcom,sde-sspp-excl-rect = <1 1>;

		qcom,sde-sspp-smart-dma-priority = <2 1>;

		qcom,sde-smart-dma-rev = "smart_dma_v2p5";



		qcom,sde-mixer-pair-mask = <0>;



		qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98

						0xb0 0xc8 0xe0 0xf8 0x110>;



		qcom,sde-mixer-stage-base-layer;



		qcom,sde-max-per-pipe-bw-kbps = <2700000 2700000>;



		qcom,sde-max-per-pipe-bw-high-kbps = <2700000 2700000>;



		/* offsets are relative to "mdp_phys + qcom,sde-off */

		qcom,sde-sspp-clk-ctrl =

				<0x2ac 0>, <0x2ac 8>;

		qcom,sde-mixer-linewidth = <2048>;

		qcom,sde-mixer-blendstages = <0x4>;

		qcom,sde-panic-per-pipe;

		qcom,sde-has-cdp;



		qcom,sde-has-dim-layer;

		qcom,sde-has-idle-pc;



		qcom,sde-max-bw-low-kbps = <2700000>;

		qcom,sde-max-bw-high-kbps = <2700000>;

		qcom,sde-min-core-ib-kbps = <1300000>;

		qcom,sde-min-llcc-ib-kbps = <0>;

		qcom,sde-min-dram-ib-kbps = <1600000>;

		qcom,sde-dram-channels = <2>;

		qcom,sde-num-nrt-paths = <0>;



		qcom,sde-vbif-off = <0>;

		qcom,sde-vbif-size = <0x2008>;

		qcom,sde-vbif-id = <0>;

		qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;

		qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;



		qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;



		/*Pending macrotile & macrotile-qseed has the same configs */



		qcom,sde-danger-lut = <0x000000ff 0x00000000

			0x00000000 0x00000000 0x00000000>;



		qcom,sde-safe-lut-linear = <0 0xfff0>;



		qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>;



		qcom,sde-cdp-setting = <1 0>;



		qcom,sde-qos-cpu-mask = <0x3>;

		qcom,sde-qos-cpu-dma-latency = <300>;



		qcom,sde-secure-sid-mask = <0x0000421>;

		qcom,sde-num-mnoc-ports = <1>;

		qcom,sde-axi-bus-width = <16>;



		qcom,sde-reg-bus,vectors-KBps = <0 0>,

				<0 76800>,

				<0 150000>,

				<0 300000>;



		qcom,sde-sspp-vig-blocks {

		};



		qcom,sde-dspp-blocks {

			qcom,sde-dspp-igc = <0x0 0x00030001>;

			qcom,sde-dspp-hsic = <0x800 0x00010007>;

			qcom,sde-dspp-memcolor = <0x880 0x00010007>;

			qcom,sde-dspp-hist = <0x800 0x00010007>;

			qcom,sde-dspp-sixzone= <0x900 0x00010007>;

			qcom,sde-dspp-vlut = <0xa00 0x00010008>;

			qcom,sde-dspp-pcc = <0x1700 0x00040000>;

			qcom,sde-dspp-gc = <0x17c0 0x00010008>;

			qcom,sde-dspp-dither = <0x82c 0x00010007>;

		};



		qcom,platform-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,platform-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "sde-vdd";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};



		/* data and reg bus scale settings */

		qcom,sde-data-bus {

			qcom,msm-bus,name = "mdss_sde";

			qcom,msm-bus,num-cases = <3>;

			qcom,msm-bus,num-paths = <1>;

			qcom,msm-bus,vectors-KBps =

				<22 512 0 0>,

				<22 512 0 4800000>,

				<22 512 0 4800000>;

		};



		qcom,sde-limits {

			qcom,sde-linewidth-limits {

				qcom,sde-limit-name = "sspp_linewidth_usecases";

				qcom,sde-limit-cases = "vig", "dma";

				qcom,sde-limit-ids= <0x1 0x2>;

				qcom,sde-limit-values = <0x1 2160>,

							<0x2 2160>;

			};



			qcom,sde-bw-limits {

				qcom,sde-limit-name = "sde_bwlimit_usecases";

				qcom,sde-limit-cases = "per_vig_pipe",

							"per_dma_pipe",

							"total_max_bw",

							"camera_concurrency";

				qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>;

				qcom,sde-limit-values = <0x1 2700000>,

							<0x9 2700000>,

							<0x2 2700000>,

							<0xa 2700000>,

							<0x4 2700000>,

							<0xc 2700000>;

			};

		};

	};



	mdss_dsi0: qcom,mdss_dsi0_ctrl {

		compatible = "qcom,dsi-ctrl-hw-v2.4";

		label = "dsi-ctrl-0";

		cell-index = <0>;

		reg =   <0x5e94000 0x400>,

			<0x5f08000 0x4>;

		reg-names = "dsi_ctrl", "disp_cc_base";

		interrupt-parent = <&mdss_mdp>;

		interrupts = <4 0>;

		vdda-1p2-supply = <&L9A>;

		clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,

			<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,

			<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,

			<&dispcc DISP_CC_MDSS_PCLK0_CLK>,

			<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,

			<&dispcc DISP_CC_MDSS_ESC0_CLK>;

		clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",

					"pixel_clk", "pixel_clk_rcg",

					"esc_clk";



		qcom,ctrl-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,ctrl-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-1p2";

				qcom,supply-min-voltage = <1232000>;

				qcom,supply-max-voltage = <1312000>;

				qcom,supply-enable-load = <21800>;

				qcom,supply-disable-load = <0>;

			};

		};



		qcom,core-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,core-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "refgen";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};



	mdss_dsi_phy0: qcom,mdss_dsi_phy0 {

		compatible = "qcom,dsi-phy-v4.2";

		label = "dsi-phy-0";

		cell-index = <0>;

		#clock-cells = <1>;

		reg = <0x5e94400 0x800>,

			<0x5e94900 0x27c>,

			<0x5e94200 0x100>,

			<0x5f03000 0x8>;

		reg-names = "dsi_phy", "pll_base", "dyn_refresh_base", "gdsc_base";

		pll-label = "dsi_pll_5nm";

		memory-region = <&dfps_data_memory>;

		vdda-0p9-supply = <&L12A>;

		/*TODO: check these*/

		qcom,platform-strength-ctrl = [ff 06

						ff 06

						ff 06

						ff 06

						ff 00];

		qcom,platform-lane-config = [00 00 10 0f

						00 00 10 0f

						00 00 10 0f

						00 00 10 0f

						00 00 10 8f];

		qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];

		qcom,panel-allow-phy-poweroff;

		qcom,dsi-pll-ssc-en;

		qcom,dsi-pll-ssc-mode = "down-spread";

		qcom,phy-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,phy-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-0p9";

				qcom,supply-min-voltage = <880000>;

				qcom,supply-max-voltage = <880000>;

				qcom,supply-enable-load = <37550>;

				qcom,supply-disable-load = <0>;

			};

		};

	};

};