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Commit 333061b9 authored by Max Uvarov's avatar Max Uvarov Committed by David S. Miller
Browse files

net: phy: dp83867: fix speed 10 in sgmii mode 



For supporting 10Mps speed in SGMII mode DP83867_10M_SGMII_RATE_ADAPT bit
of DP83867_10M_SGMII_CFG register has to be cleared by software.
That does not affect speeds 100 and 1000 so can be done on init.

Signed-off-by: default avatarMax Uvarov <muvarov@gmail.com>
Cc: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3d3ced2e

drivers/net/phy/dp83867.c

+17 −0
Original line number Diff line number Diff line
@@ -30,6 +30,8 @@ 
#define DP83867_STRAP_STS1	0x006E

#define DP83867_RGMIIDCTL	0x0086

#define DP83867_IO_MUX_CFG	0x0170

#define DP83867_10M_SGMII_CFG   0x016F

#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)



#define DP83867_SW_RESET	BIT(15)

#define DP83867_SW_RESTART	BIT(14)
@@ -277,6 +279,21 @@ static int dp83867_config_init(struct phy_device *phydev) 
				       DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL);

	}



	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {

		/* For support SPEED_10 in SGMII mode

		 * DP83867_10M_SGMII_RATE_ADAPT bit

		 * has to be cleared by software. That

		 * does not affect SPEED_100 and

		 * SPEED_1000.

		 */

		ret = phy_modify_mmd(phydev, DP83867_DEVADDR,

				     DP83867_10M_SGMII_CFG,

				     DP83867_10M_SGMII_RATE_ADAPT_MASK,

				     0);

		if (ret)

			return ret;

	}



	/* Enable Interrupt output INT_OE in CFG3 register */

	if (phy_interrupt_is_valid(phydev)) {

		val = phy_read(phydev, DP83867_CFG3);