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Commit 324513c0 authored by Imre Deak's avatar Imre Deak
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drm/i915/bxt: Rename broxton to bxt in PHY/CDCLK function prefixes 



Rename these remaining function prefixes to better align with the
corresponding SKL functions.

No functional change.

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
parent 95a7a2ae

drivers/gpu/drm/i915/intel_ddi.c

+6 −7
Original line number Diff line number Diff line
@@ -1773,14 +1773,14 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, 
	return true;

}



static u32 broxton_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)

static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)

{

	u32 val = I915_READ(BXT_PORT_REF_DW6(phy));



	return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;

}



static void broxton_phy_wait_grc_done(struct drm_i915_private *dev_priv,

static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,

				  enum dpio_phy phy)

{

	if (wait_for(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE, 10))
@@ -1794,7 +1794,7 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy) 
	if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {

		/* Still read out the GRC value for state verification */

		if (phy == DPIO_PHY0)

			dev_priv->bxt_phy_grc = broxton_get_grc(dev_priv, phy);

			dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);



		if (bxt_ddi_phy_verify_state(dev_priv, phy)) {

			DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
@@ -1870,8 +1870,7 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy) 
		 * the corresponding calibrated value from PHY1, and disable

		 * the automatic calibration on PHY0.

		 */

		val = dev_priv->bxt_phy_grc = broxton_get_grc(dev_priv,

							      DPIO_PHY1);

		val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1);

		grc_code = val << GRC_CODE_FAST_SHIFT |

			   val << GRC_CODE_SLOW_SHIFT |

			   val;
@@ -1887,7 +1886,7 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy) 
	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);



	if (phy == DPIO_PHY1)

		broxton_phy_wait_grc_done(dev_priv, DPIO_PHY1);

		bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1);

}



void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)

drivers/gpu/drm/i915/intel_display.c

+14 −14
Original line number Diff line number Diff line
@@ -123,7 +123,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc); 
static void intel_modeset_setup_hw_state(struct drm_device *dev);

static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);

static int ilk_max_pixel_rate(struct drm_atomic_state *state);

static int broxton_calc_cdclk(int max_pixclk);

static int bxt_calc_cdclk(int max_pixclk);



struct intel_limit {

	struct {
@@ -5420,7 +5420,7 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) 
	dev_priv->cdclk_pll.vco = vco;

}



static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)

static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)

{

	u32 val, divider;

	int vco, ret;
@@ -5545,7 +5545,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 
	dev_priv->cdclk_pll.vco = -1;

}



void broxton_init_cdclk(struct drm_i915_private *dev_priv)

void bxt_init_cdclk(struct drm_i915_private *dev_priv)

{

	bxt_sanitize_cdclk(dev_priv);
@@ -5557,12 +5557,12 @@ void broxton_init_cdclk(struct drm_i915_private *dev_priv) 
	 * - The initial CDCLK needs to be read from VBT.

	 *   Need to make this change after VBT has changes for BXT.

	 */

	broxton_set_cdclk(dev_priv, broxton_calc_cdclk(0));

	bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));

}



void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)

void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)

{

	broxton_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);

	bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);

}



static int skl_calc_cdclk(int max_pixclk, int vco)
@@ -5988,7 +5988,7 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, 
		return 200000;

}



static int broxton_calc_cdclk(int max_pixclk)

static int bxt_calc_cdclk(int max_pixclk)

{

	if (max_pixclk > 576000)

		return 624000;
@@ -6048,17 +6048,17 @@ static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) 
	return 0;

}



static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)

static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)

{

	int max_pixclk = ilk_max_pixel_rate(state);

	struct intel_atomic_state *intel_state =

		to_intel_atomic_state(state);



	intel_state->cdclk = intel_state->dev_cdclk =

		broxton_calc_cdclk(max_pixclk);

		bxt_calc_cdclk(max_pixclk);



	if (!intel_state->active_crtcs)

		intel_state->dev_cdclk = broxton_calc_cdclk(0);

		intel_state->dev_cdclk = bxt_calc_cdclk(0);



	return 0;

}
@@ -9654,14 +9654,14 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv) 
	}

}



static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)

static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)

{

	struct drm_device *dev = old_state->dev;

	struct intel_atomic_state *old_intel_state =

		to_intel_atomic_state(old_state);

	unsigned int req_cdclk = old_intel_state->dev_cdclk;



	broxton_set_cdclk(to_i915(dev), req_cdclk);

	bxt_set_cdclk(to_i915(dev), req_cdclk);

}



/* compute the max rate for new configuration */
@@ -15206,9 +15206,9 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) 
			valleyview_modeset_calc_cdclk;

	} else if (IS_BROXTON(dev_priv)) {

		dev_priv->display.modeset_commit_cdclk =

			broxton_modeset_commit_cdclk;

			bxt_modeset_commit_cdclk;

		dev_priv->display.modeset_calc_cdclk =

			broxton_modeset_calc_cdclk;

			bxt_modeset_calc_cdclk;

	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

		dev_priv->display.modeset_commit_cdclk =

			skl_modeset_commit_cdclk;

drivers/gpu/drm/i915/intel_drv.h

+2 −2
Original line number Diff line number Diff line
@@ -1267,8 +1267,8 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv); 
void intel_finish_reset(struct drm_i915_private *dev_priv);

void hsw_enable_pc8(struct drm_i915_private *dev_priv);

void hsw_disable_pc8(struct drm_i915_private *dev_priv);

void broxton_init_cdclk(struct drm_i915_private *dev_priv);

void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);

void bxt_init_cdclk(struct drm_i915_private *dev_priv);

void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);

void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);

void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);

bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/intel_runtime_pm.c

+2 −2
Original line number Diff line number Diff line
@@ -2401,7 +2401,7 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv, 


	mutex_unlock(&power_domains->lock);



	broxton_init_cdclk(dev_priv);

	bxt_init_cdclk(dev_priv);



	gen9_dbuf_enable(dev_priv);
@@ -2418,7 +2418,7 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv) 


	gen9_dbuf_disable(dev_priv);



	broxton_uninit_cdclk(dev_priv);

	bxt_uninit_cdclk(dev_priv);



	/* The spec doesn't call for removing the reset handshake flag */