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Commit 31f46717 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 

* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
  agp: amd64, fix pci reference leaks
  drm/edid: Allow non-fatal checksum errors in CEA blocks
  drm/radeon/kms: suppress a build warning (unused variable)
  drm: Fixes linux-next & linux-2.6 checkstack warnings:
  nouveau: fix acpi_lid_open undefined
  drm/radeon/kms: release AGP bridge at suspend
parents 91803b49 2101d6f7

drivers/char/agp/amd64-agp.c

+18 −10
Original line number Original line Diff line number Diff line
@@ -384,7 +384,7 @@ static int __devinit uli_agp_init(struct pci_dev *pdev) 
{

{

	u32 httfea,baseaddr,enuscr;

	u32 httfea,baseaddr,enuscr;

	struct pci_dev *dev1;

	struct pci_dev *dev1;

	int i;

	int i, ret;

	unsigned size = amd64_fetch_size();

	unsigned size = amd64_fetch_size();





	dev_info(&pdev->dev, "setting up ULi AGP\n");

	dev_info(&pdev->dev, "setting up ULi AGP\n");
@@ -400,15 +400,18 @@ static int __devinit uli_agp_init(struct pci_dev *pdev) 




	if (i == ARRAY_SIZE(uli_sizes)) {

	if (i == ARRAY_SIZE(uli_sizes)) {

		dev_info(&pdev->dev, "no ULi size found for %d\n", size);

		dev_info(&pdev->dev, "no ULi size found for %d\n", size);

		return -ENODEV;

		ret = -ENODEV;

		goto put;

	}

	}





	/* shadow x86-64 registers into ULi registers */

	/* shadow x86-64 registers into ULi registers */

	pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea);

	pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea);





	/* if x86-64 aperture base is beyond 4G, exit here */

	/* if x86-64 aperture base is beyond 4G, exit here */

	if ((httfea & 0x7fff) >> (32 - 25))

	if ((httfea & 0x7fff) >> (32 - 25)) {

		return -ENODEV;

		ret = -ENODEV;

		goto put;

	}





	httfea = (httfea& 0x7fff) << 25;

	httfea = (httfea& 0x7fff) << 25;
@@ -420,9 +423,10 @@ static int __devinit uli_agp_init(struct pci_dev *pdev) 
	enuscr= httfea+ (size * 1024 * 1024) - 1;

	enuscr= httfea+ (size * 1024 * 1024) - 1;

	pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);

	pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);

	pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);

	pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);



	ret = 0;

put:

	pci_dev_put(dev1);

	pci_dev_put(dev1);

	return 0;

	return ret;

}

}
@@ -441,7 +445,7 @@ static int nforce3_agp_init(struct pci_dev *pdev) 
{

{

	u32 tmp, apbase, apbar, aplimit;

	u32 tmp, apbase, apbar, aplimit;

	struct pci_dev *dev1;

	struct pci_dev *dev1;

	int i;

	int i, ret;

	unsigned size = amd64_fetch_size();

	unsigned size = amd64_fetch_size();





	dev_info(&pdev->dev, "setting up Nforce3 AGP\n");

	dev_info(&pdev->dev, "setting up Nforce3 AGP\n");
@@ -458,7 +462,8 @@ static int nforce3_agp_init(struct pci_dev *pdev) 




	if (i == ARRAY_SIZE(nforce3_sizes)) {

	if (i == ARRAY_SIZE(nforce3_sizes)) {

		dev_info(&pdev->dev, "no NForce3 size found for %d\n", size);

		dev_info(&pdev->dev, "no NForce3 size found for %d\n", size);

		return -ENODEV;

		ret = -ENODEV;

		goto put;

	}

	}





	pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);

	pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
@@ -472,7 +477,8 @@ static int nforce3_agp_init(struct pci_dev *pdev) 
	/* if x86-64 aperture base is beyond 4G, exit here */

	/* if x86-64 aperture base is beyond 4G, exit here */

	if ( (apbase & 0x7fff) >> (32 - 25) ) {

	if ( (apbase & 0x7fff) >> (32 - 25) ) {

		dev_info(&pdev->dev, "aperture base > 4G\n");

		dev_info(&pdev->dev, "aperture base > 4G\n");

		return -ENODEV;

		ret = -ENODEV;

		goto put;

	}

	}





	apbase = (apbase & 0x7fff) << 25;

	apbase = (apbase & 0x7fff) << 25;
@@ -488,9 +494,11 @@ static int nforce3_agp_init(struct pci_dev *pdev) 
	pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);

	pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);

	pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);

	pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);





	ret = 0;

put:

	pci_dev_put(dev1);

	pci_dev_put(dev1);





	return 0;

	return ret;

}

}





static int __devinit agp_amd64_probe(struct pci_dev *pdev,

static int __devinit agp_amd64_probe(struct pci_dev *pdev,

drivers/gpu/drm/drm_edid.c

+4 −1
Original line number Original line Diff line number Diff line
@@ -147,6 +147,9 @@ drm_edid_block_valid(u8 *raw_edid) 
		csum += raw_edid[i];

		csum += raw_edid[i];

	if (csum) {

	if (csum) {

		DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);

		DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);



		/* allow CEA to slide through, switches mangle this */

		if (raw_edid[0] != 0x02)

			goto bad;

			goto bad;

	}

	}

drivers/gpu/drm/nouveau/nouveau_connector.c

+2 −1
Original line number Original line Diff line number Diff line
@@ -241,7 +241,8 @@ nouveau_connector_detect(struct drm_connector *connector) 
	if (nv_encoder && nv_connector->native_mode) {

	if (nv_encoder && nv_connector->native_mode) {

		unsigned status = connector_status_connected;

		unsigned status = connector_status_connected;





#ifdef CONFIG_ACPI

#if defined(CONFIG_ACPI_BUTTON) || \

	(defined(CONFIG_ACPI_BUTTON_MODULE) && defined(MODULE))

		if (!nouveau_ignorelid && !acpi_lid_open())

		if (!nouveau_ignorelid && !acpi_lid_open())

			status = connector_status_unknown;

			status = connector_status_unknown;

#endif

#endif

drivers/gpu/drm/nouveau/nv40_graph.c

+7 −1
Original line number Original line Diff line number Diff line
@@ -253,7 +253,11 @@ nv40_graph_init(struct drm_device *dev) 




	if (!dev_priv->engine.graph.ctxprog) {

	if (!dev_priv->engine.graph.ctxprog) {

		struct nouveau_grctx ctx = {};

		struct nouveau_grctx ctx = {};

		uint32_t cp[256];

		uint32_t *cp;



		cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);

		if (!cp)

			return -ENOMEM;





		ctx.dev = dev;

		ctx.dev = dev;

		ctx.mode = NOUVEAU_GRCTX_PROG;

		ctx.mode = NOUVEAU_GRCTX_PROG;
@@ -265,6 +269,8 @@ nv40_graph_init(struct drm_device *dev) 
		nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);

		nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);

		for (i = 0; i < ctx.ctxprog_len; i++)

		for (i = 0; i < ctx.ctxprog_len; i++)

			nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);

			nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);



		kfree(cp);

	}

	}





	/* No context present currently */

	/* No context present currently */

drivers/gpu/drm/radeon/atombios_crtc.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -707,6 +707,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode 
		break;

		break;

	case ATOM_DCPLL:

	case ATOM_DCPLL:

	case ATOM_PPLL_INVALID:

	case ATOM_PPLL_INVALID:

	default:

		pll = &rdev->clock.dcpll;

		pll = &rdev->clock.dcpll;

		break;

		break;

	}

	}