drm/amd/powerplay: add avfs related define for polaris (31b21243) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/gpu/drm/amd/powerplay/inc/smu74.h

+67 −8

Original line number	Original line	Diff line number	Diff line
	@@ -34,6 +34,30 @@
	#define SMU__NUM_LCLK_DPM_LEVELS 8		#define SMU__NUM_LCLK_DPM_LEVELS 8
	#define SMU__NUM_PCIE_DPM_LEVELS 8		#define SMU__NUM_PCIE_DPM_LEVELS 8

			#define EXP_M1 35
			#define EXP_M2 92821
			#define EXP_B 66629747

			#define EXP_M1_1 365
			#define EXP_M2_1 658700
			#define EXP_B_1 305506134

			#define EXP_M1_2 189
			#define EXP_M2_2 379692
			#define EXP_B_2 194609469

			#define EXP_M1_3 99
			#define EXP_M2_3 217915
			#define EXP_B_3 122255994

			#define EXP_M1_4 51
			#define EXP_M2_4 122643
			#define EXP_B_4 74893384

			#define EXP_M1_5 423
			#define EXP_M2_5 1103326
			#define EXP_B_5 728122621

	enum SID_OPTION {		enum SID_OPTION {
	SID_OPTION_HI,		SID_OPTION_HI,
	SID_OPTION_LO,		SID_OPTION_LO,
	@@ -548,20 +572,20 @@ struct SMU74_Firmware_Header {
	uint32_t CacConfigTable;		uint32_t CacConfigTable;
	uint32_t CacStatusTable;		uint32_t CacStatusTable;


	uint32_t mcRegisterTable;		uint32_t mcRegisterTable;


	uint32_t mcArbDramTimingTable;		uint32_t mcArbDramTimingTable;




	uint32_t PmFuseTable;		uint32_t PmFuseTable;
	uint32_t Globals;		uint32_t Globals;
	uint32_t ClockStretcherTable;		uint32_t ClockStretcherTable;
	uint32_t VftTable;		uint32_t VftTable;
	uint32_t Reserved[21];		uint32_t Reserved1;
			uint32_t AvfsTable;
			uint32_t AvfsCksOffGbvTable;
			uint32_t AvfsMeanNSigma;
			uint32_t AvfsSclkOffsetTable;
			uint32_t Reserved[16];
	uint32_t Signature;		uint32_t Signature;
	};		};

	@@ -701,8 +725,6 @@ VR Config info is contained in dpmTable.VRConfig */
	struct SMU_ClockStretcherDataTableEntry {		struct SMU_ClockStretcherDataTableEntry {
	uint8_t minVID;		uint8_t minVID;
	uint8_t maxVID;		uint8_t maxVID;


	uint16_t setting;		uint16_t setting;
	};		};
	typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;		typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
	@@ -769,6 +791,43 @@ struct VFT_TABLE_t {
	typedef struct VFT_TABLE_t VFT_TABLE_t;		typedef struct VFT_TABLE_t VFT_TABLE_t;


			/* Total margin, root mean square of Fmax + DC + Platform */
			struct AVFS_Margin_t {
			VFT_CELL_t Cell[NUM_VFT_COLUMNS];
			};
			typedef struct AVFS_Margin_t AVFS_Margin_t;

			#define BTCGB_VDROOP_TABLE_MAX_ENTRIES 2
			#define AVFSGB_VDROOP_TABLE_MAX_ENTRIES 2

			struct GB_VDROOP_TABLE_t {
			int32_t a0;
			int32_t a1;
			int32_t a2;
			uint32_t spare;
			};
			typedef struct GB_VDROOP_TABLE_t GB_VDROOP_TABLE_t;

			struct AVFS_CksOff_Gbv_t {
			VFT_CELL_t Cell[NUM_VFT_COLUMNS];
			};
			typedef struct AVFS_CksOff_Gbv_t AVFS_CksOff_Gbv_t;

			struct AVFS_meanNsigma_t {
			uint32_t Aconstant[3];
			uint16_t DC_tol_sigma;
			uint16_t Platform_mean;
			uint16_t Platform_sigma;
			uint16_t PSM_Age_CompFactor;
			uint8_t Static_Voltage_Offset[NUM_VFT_COLUMNS];
			};
			typedef struct AVFS_meanNsigma_t AVFS_meanNsigma_t;

			struct AVFS_Sclk_Offset_t {
			uint16_t Sclk_Offset[8];
			};
			typedef struct AVFS_Sclk_Offset_t AVFS_Sclk_Offset_t;

	#endif		#endif

drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h

+31 −11

Original line number	Original line	Diff line number	Diff line
	@@ -223,6 +223,16 @@ struct SMU74_Discrete_StateInfo {

	typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo;		typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo;

			struct SMU_QuadraticCoeffs {
			int32_t m1;
			uint32_t b;

			int16_t m2;
			uint8_t m1_shift;
			uint8_t m2_shift;
			};
			typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;

	struct SMU74_Discrete_DpmTable {		struct SMU74_Discrete_DpmTable {

	SMU74_PIDController GraphicsPIDController;		SMU74_PIDController GraphicsPIDController;
	@@ -258,7 +268,14 @@ struct SMU74_Discrete_DpmTable {
	uint8_t ThermOutPolarity;		uint8_t ThermOutPolarity;
	uint8_t ThermOutMode;		uint8_t ThermOutMode;
	uint8_t BootPhases;		uint8_t BootPhases;
	uint32_t Reserved[4];
			uint8_t VRHotLevel;
			uint8_t Reserved1[3];
			uint16_t FanStartTemperature;
			uint16_t FanStopTemperature;
			uint16_t MaxVoltage;
			uint16_t Reserved2;
			uint32_t Reserved[1];

	SMU74_Discrete_GraphicsLevel GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS];		SMU74_Discrete_GraphicsLevel GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS];
	SMU74_Discrete_MemoryLevel MemoryACPILevel;		SMU74_Discrete_MemoryLevel MemoryACPILevel;
	@@ -347,6 +364,8 @@ struct SMU74_Discrete_DpmTable {

	uint32_t CurrSclkPllRange;		uint32_t CurrSclkPllRange;
	sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE];		sclkFcwRange_t SclkFcwRangeTable[NUM_SCLK_RANGE];
			GB_VDROOP_TABLE_t BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES];
			SMU_QuadraticCoeffs AVFSGB_VDROOP_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES];
	};		};

	typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable;		typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable;
	@@ -550,16 +569,6 @@ struct SMU7_AcpiScoreboard {

	typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;		typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;

	struct SMU_QuadraticCoeffs {
	int32_t m1;
	uint32_t b;

	int16_t m2;
	uint8_t m1_shift;
	uint8_t m2_shift;
	};
	typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;

	struct SMU74_Discrete_PmFuses {		struct SMU74_Discrete_PmFuses {
	uint8_t BapmVddCVidHiSidd[8];		uint8_t BapmVddCVidHiSidd[8];
	uint8_t BapmVddCVidLoSidd[8];		uint8_t BapmVddCVidLoSidd[8];
	@@ -821,6 +830,17 @@ typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
	#define DB_PCC_SHIFT 26		#define DB_PCC_SHIFT 26
	#define DB_EDC_SHIFT 27		#define DB_EDC_SHIFT 27

			#define BTCGB0_Vdroop_Enable_MASK 0x1
			#define BTCGB1_Vdroop_Enable_MASK 0x2
			#define AVFSGB0_Vdroop_Enable_MASK 0x4
			#define AVFSGB1_Vdroop_Enable_MASK 0x8

			#define BTCGB0_Vdroop_Enable_SHIFT 0
			#define BTCGB1_Vdroop_Enable_SHIFT 1
			#define AVFSGB0_Vdroop_Enable_SHIFT 2
			#define AVFSGB1_Vdroop_Enable_SHIFT 3


	#pragma pack(pop)		#pragma pack(pop)