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Commit 31855d74 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 5.4.182 into android11-5.4-lts 



Changes in 5.4.182
	cgroup/cpuset: Fix a race between cpuset_attach() and cpu hotplug
	clk: jz4725b: fix mmc0 clock gating
	vhost/vsock: don't check owner in vhost_vsock_stop() while releasing
	parisc/unaligned: Fix fldd and fstd unaligned handlers on 32-bit kernel
	parisc/unaligned: Fix ldw() and stw() unalignment handlers
	drm/amdgpu: disable MMHUB PG for Picasso
	sr9700: sanity check for packet length
	USB: zaurus: support another broken Zaurus
	netfilter: nf_tables_offload: incorrect flow offload action array size
	x86/fpu: Correct pkru/xstate inconsistency
	tee: export teedev_open() and teedev_close_context()
	optee: use driver internal tee_context for some rpc
	lan743x: fix deadlock in lan743x_phy_link_status_change()
	ping: remove pr_err from ping_lookup
	perf data: Fix double free in perf_session__delete()
	bpf: Do not try bpf_msg_push_data with len 0
	net: __pskb_pull_tail() & pskb_carve_frag_list() drop_monitor friends
	tipc: Fix end of loop tests for list_for_each_entry()
	gso: do not skip outer ip header in case of ipip and net_failover
	openvswitch: Fix setting ipv6 fields causing hw csum failure
	drm/edid: Always set RGB444
	net/mlx5e: Fix wrong return value on ioctl EEPROM query failure
	net: ll_temac: check the return value of devm_kmalloc()
	net: Force inlining of checksum functions in net/checksum.h
	nfp: flower: Fix a potential leak in nfp_tunnel_add_shared_mac()
	netfilter: nf_tables: fix memory leak during stateful obj update
	net/mlx5: Fix possible deadlock on rule deletion
	net/mlx5: Fix wrong limitation of metadata match on ecpf
	spi: spi-zynq-qspi: Fix a NULL pointer dereference in zynq_qspi_exec_mem_op()
	configfs: fix a race in configfs_{,un}register_subsystem()
	RDMA/ib_srp: Fix a deadlock
	tracing: Have traceon and traceoff trigger honor the instance
	iio: adc: men_z188_adc: Fix a resource leak in an error handling path
	iio: adc: ad7124: fix mask used for setting AIN_BUFP & AIN_BUFM bits
	iio: Fix error handling for PM
	ata: pata_hpt37x: disable primary channel on HPT371
	Revert "USB: serial: ch341: add new Product ID for CH341A"
	usb: gadget: rndis: add spinlock for rndis response list
	USB: gadget: validate endpoint index for xilinx udc
	tracefs: Set the group ownership in apply_options() not parse_options()
	USB: serial: option: add support for DW5829e
	USB: serial: option: add Telit LE910R1 compositions
	usb: dwc3: pci: Fix Bay Trail phy GPIO mappings
	usb: dwc3: gadget: Let the interrupt handler disable bottom halves.
	xhci: re-initialize the HC during resume if HCE was set
	xhci: Prevent futile URB re-submissions due to incorrect return value.
	tty: n_gsm: fix encoding of control signal octet bit DV
	tty: n_gsm: fix proper link termination after failed open
	tty: n_gsm: fix NULL pointer access due to DLCI release
	gpio: tegra186: Fix chip_data type confusion
	Revert "drm/nouveau/pmu/gm200-: avoid touching PMU outside of DEVINIT/PREOS/ACR"
	memblock: use kfree() to release kmalloced memblock regions
	fget: clarify and improve __fget_files() implementation
	Linux 5.4.182

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
Change-Id: Ied5808972eaee5c321a5e11c5220d51a4f8e1a60
parents 2867afd6 866ae42c

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 5

PATCHLEVEL = 4

SUBLEVEL = 181

SUBLEVEL = 182

EXTRAVERSION =

NAME = Kleptomaniac Octopus

arch/parisc/kernel/unaligned.c

+7 −7
Original line number Diff line number Diff line
@@ -340,7 +340,7 @@ static int emulate_stw(struct pt_regs *regs, int frreg, int flop) 
	: "r" (val), "r" (regs->ior), "r" (regs->isr)

	: "r19", "r20", "r21", "r22", "r1", FIXUP_BRANCH_CLOBBER );



	return 0;

	return ret;

}

static int emulate_std(struct pt_regs *regs, int frreg, int flop)

{
@@ -397,7 +397,7 @@ static int emulate_std(struct pt_regs *regs, int frreg, int flop) 
	__asm__ __volatile__ (

"	mtsp	%4, %%sr1\n"

"	zdep	%2, 29, 2, %%r19\n"

"	dep	%%r0, 31, 2, %2\n"

"	dep	%%r0, 31, 2, %3\n"

"	mtsar	%%r19\n"

"	zvdepi	-2, 32, %%r19\n"

"1:	ldw	0(%%sr1,%3),%%r20\n"
@@ -409,7 +409,7 @@ static int emulate_std(struct pt_regs *regs, int frreg, int flop) 
"	andcm	%%r21, %%r19, %%r21\n"

"	or	%1, %%r20, %1\n"

"	or	%2, %%r21, %2\n"

"3:	stw	%1,0(%%sr1,%1)\n"

"3:	stw	%1,0(%%sr1,%3)\n"

"4:	stw	%%r1,4(%%sr1,%3)\n"

"5:	stw	%2,8(%%sr1,%3)\n"

"	copy	%%r0, %0\n"
@@ -596,7 +596,6 @@ void handle_unaligned(struct pt_regs *regs) 
		ret = ERR_NOTHANDLED;	/* "undefined", but lets kill them. */

		break;

	}

#ifdef CONFIG_PA20

	switch (regs->iir & OPCODE2_MASK)

	{

	case OPCODE_FLDD_L:
@@ -607,22 +606,23 @@ void handle_unaligned(struct pt_regs *regs) 
		flop=1;

		ret = emulate_std(regs, R2(regs->iir),1);

		break;

#ifdef CONFIG_PA20

	case OPCODE_LDD_L:

		ret = emulate_ldd(regs, R2(regs->iir),0);

		break;

	case OPCODE_STD_L:

		ret = emulate_std(regs, R2(regs->iir),0);

		break;

	}

#endif

	}

	switch (regs->iir & OPCODE3_MASK)

	{

	case OPCODE_FLDW_L:

		flop=1;

		ret = emulate_ldw(regs, R2(regs->iir),0);

		ret = emulate_ldw(regs, R2(regs->iir), 1);

		break;

	case OPCODE_LDW_M:

		ret = emulate_ldw(regs, R2(regs->iir),1);

		ret = emulate_ldw(regs, R2(regs->iir), 0);

		break;



	case OPCODE_FSTW_L:

arch/x86/include/asm/fpu/internal.h

+8 −5
Original line number Diff line number Diff line
@@ -560,9 +560,11 @@ static inline void __fpregs_load_activate(void) 
 * The FPU context is only stored/restored for a user task and

 * PF_KTHREAD is used to distinguish between kernel and user threads.

 */

static inline void switch_fpu_prepare(struct fpu *old_fpu, int cpu)

static inline void switch_fpu_prepare(struct task_struct *prev, int cpu)

{

	if (static_cpu_has(X86_FEATURE_FPU) && !(current->flags & PF_KTHREAD)) {

	struct fpu *old_fpu = &prev->thread.fpu;



	if (static_cpu_has(X86_FEATURE_FPU) && !(prev->flags & PF_KTHREAD)) {

		if (!copy_fpregs_to_fpstate(old_fpu))

			old_fpu->last_cpu = -1;

		else
@@ -581,10 +583,11 @@ static inline void switch_fpu_prepare(struct fpu *old_fpu, int cpu) 
 * Load PKRU from the FPU context if available. Delay loading of the

 * complete FPU state until the return to userland.

 */

static inline void switch_fpu_finish(struct fpu *new_fpu)

static inline void switch_fpu_finish(struct task_struct *next)

{

	u32 pkru_val = init_pkru_value;

	struct pkru_state *pk;

	struct fpu *next_fpu = &next->thread.fpu;



	if (!static_cpu_has(X86_FEATURE_FPU))

		return;
@@ -598,7 +601,7 @@ static inline void switch_fpu_finish(struct fpu *new_fpu) 
	 * PKRU state is switched eagerly because it needs to be valid before we

	 * return to userland e.g. for a copy_to_user() operation.

	 */

	if (!(current->flags & PF_KTHREAD)) {

	if (!(next->flags & PF_KTHREAD)) {

		/*

		 * If the PKRU bit in xsave.header.xfeatures is not set,

		 * then the PKRU component was in init state, which means
@@ -607,7 +610,7 @@ static inline void switch_fpu_finish(struct fpu *new_fpu) 
		 * in memory is not valid. This means pkru_val has to be

		 * set to 0 and not to init_pkru_value.

		 */

		pk = get_xsave_addr(&new_fpu->state.xsave, XFEATURE_PKRU);

		pk = get_xsave_addr(&next_fpu->state.xsave, XFEATURE_PKRU);

		pkru_val = pk ? pk->pkru : 0;

	}

	__write_pkru(pkru_val);

arch/x86/kernel/process_32.c

+2 −4
Original line number Diff line number Diff line
@@ -229,14 +229,12 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) 
{

	struct thread_struct *prev = &prev_p->thread,

			     *next = &next_p->thread;

	struct fpu *prev_fpu = &prev->fpu;

	struct fpu *next_fpu = &next->fpu;

	int cpu = smp_processor_id();



	/* never put a printk in __switch_to... printk() calls wake_up*() indirectly */



	if (!test_thread_flag(TIF_NEED_FPU_LOAD))

		switch_fpu_prepare(prev_fpu, cpu);

		switch_fpu_prepare(prev_p, cpu);



	/*

	 * Save away %gs. No need to save %fs, as it was saved on the
@@ -292,7 +290,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) 


	this_cpu_write(current_task, next_p);



	switch_fpu_finish(next_fpu);

	switch_fpu_finish(next_p);



	/* Load the Intel cache allocation PQR MSR. */

	resctrl_sched_in();

arch/x86/kernel/process_64.c

+2 −4
Original line number Diff line number Diff line
@@ -505,15 +505,13 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) 
{

	struct thread_struct *prev = &prev_p->thread;

	struct thread_struct *next = &next_p->thread;

	struct fpu *prev_fpu = &prev->fpu;

	struct fpu *next_fpu = &next->fpu;

	int cpu = smp_processor_id();



	WARN_ON_ONCE(IS_ENABLED(CONFIG_DEBUG_ENTRY) &&

		     this_cpu_read(irq_count) != -1);



	if (!test_thread_flag(TIF_NEED_FPU_LOAD))

		switch_fpu_prepare(prev_fpu, cpu);

		switch_fpu_prepare(prev_p, cpu);



	/* We must save %fs and %gs before load_TLS() because

	 * %fs and %gs may be cleared by load_TLS().
@@ -565,7 +563,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) 
	this_cpu_write(current_task, next_p);

	this_cpu_write(cpu_current_top_of_stack, task_top_of_stack(next_p));



	switch_fpu_finish(next_fpu);

	switch_fpu_finish(next_p);



	/* Reload sp0. */

	update_task_stack(next_p);