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Commit 316ad4be authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue 



Jeff Kirsher says:

====================
Intel Wired LAN Driver Updates 2015-03-13

This series contains updates to ixgbe and ixgbevf.

Don adds additional support for X550 MAC types, which require additional
steps around enabling and disabling Rx.  Also cleans up variable type
inconsistency.

I provide a patch to allow relaxed ordering to be enabled on SPARC
architectures.  Also cleans up ixgbevf whitespace and code comments to
align the driver with networking coding standard.  Lastly cleaned up
uses of memcpy() where ether_addr_copy() could have been used.

Alex removes some dead code in the ixgbe cleanup patch.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 6922022a 0d8bb414

drivers/net/ethernet/intel/ixgbe/ixgbe.h

+0 −1
Original line number Diff line number Diff line
@@ -613,7 +613,6 @@ struct ixgbe_adapter { 
#define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 4)

#define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 5)

#define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 6)

#define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 7)

#define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 8)

#define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 9)

#define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 10)

drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c

+8 −2
Original line number Diff line number Diff line
@@ -171,17 +171,21 @@ static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) 
 *  @hw: pointer to hardware structure

 *

 *  Starts the hardware using the generic start_hw function.

 *  Disables relaxed ordering Then set pcie completion timeout

 *  Disables relaxed ordering for archs other than SPARC

 *  Then set pcie completion timeout

 *

 **/

static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)

{

#ifndef CONFIG_SPARC

	u32 regval;

	u32 i;

#endif

	s32 ret_val;



	ret_val = ixgbe_start_hw_generic(hw);



#ifndef CONFIG_SPARC

	/* Disable relaxed ordering */

	for (i = 0; ((i < hw->mac.max_tx_queues) &&

	     (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
@@ -197,7 +201,7 @@ static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) 
			    IXGBE_DCA_RXCTRL_HEAD_WRO_EN);

		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);

	}



#endif

	if (ret_val)

		return ret_val;
@@ -1193,6 +1197,8 @@ static struct ixgbe_mac_operations mac_ops_82598 = { 
	.init_thermal_sensor_thresh = NULL,

	.prot_autoc_read	= &prot_autoc_read_generic,

	.prot_autoc_write	= &prot_autoc_write_generic,

	.enable_rx		= &ixgbe_enable_rx_generic,

	.disable_rx		= &ixgbe_disable_rx_generic,

};



static struct ixgbe_eeprom_operations eeprom_ops_82598 = {

drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c

+6 −1
Original line number Diff line number Diff line
@@ -1977,7 +1977,10 @@ static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) 
	 */

	hw->mac.ops.disable_rx_buff(hw);



	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);

	if (regval & IXGBE_RXCTRL_RXEN)

		hw->mac.ops.enable_rx(hw);

	else

		hw->mac.ops.disable_rx(hw);



	hw->mac.ops.enable_rx_buff(hw);
@@ -2336,6 +2339,8 @@ static struct ixgbe_mac_operations mac_ops_82599 = { 
	.init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic,

	.prot_autoc_read	= &prot_autoc_read_82599,

	.prot_autoc_write	= &prot_autoc_write_82599,

	.enable_rx		= &ixgbe_enable_rx_generic,

	.disable_rx		= &ixgbe_disable_rx_generic,

};



static struct ixgbe_eeprom_operations eeprom_ops_82599 = {

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

+52 −4
Original line number Diff line number Diff line
@@ -312,7 +312,6 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 
s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)

{

	u32 i;

	u32 regval;



	/* Clear the rate limiters */

	for (i = 0; i < hw->mac.max_tx_queues; i++) {
@@ -321,20 +320,25 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 
	}

	IXGBE_WRITE_FLUSH(hw);



#ifndef CONFIG_SPARC

	/* Disable relaxed ordering */

	for (i = 0; i < hw->mac.max_tx_queues; i++) {

		u32 regval;



		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));

		regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;

		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);

	}



	for (i = 0; i < hw->mac.max_rx_queues; i++) {

		u32 regval;



		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));

		regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |

			    IXGBE_DCA_RXCTRL_HEAD_WRO_EN);

		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);

	}



#endif

	return 0;

}
@@ -703,7 +707,7 @@ s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 
	hw->adapter_stopped = true;



	/* Disable the receive unit */

	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);

	hw->mac.ops.disable_rx(hw);



	/* Clear interrupt mask to stop interrupts from being generated */

	IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
@@ -2639,7 +2643,10 @@ s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) 
 **/

s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)

{

	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);

	if (regval & IXGBE_RXCTRL_RXEN)

		hw->mac.ops.enable_rx(hw);

	else

		hw->mac.ops.disable_rx(hw);



	return 0;

}
@@ -3850,3 +3857,44 @@ s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) 
	return 0;

}



void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)

{

	u32 rxctrl;



	rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);

	if (rxctrl & IXGBE_RXCTRL_RXEN) {

		if (hw->mac.type != ixgbe_mac_82598EB) {

			u32 pfdtxgswc;



			pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);

			if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {

				pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;

				IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);

				hw->mac.set_lben = true;

			} else {

				hw->mac.set_lben = false;

			}

		}

		rxctrl &= ~IXGBE_RXCTRL_RXEN;

		IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);

	}

}



void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)

{

	u32 rxctrl;



	rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);

	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));



	if (hw->mac.type != ixgbe_mac_82598EB) {

		if (hw->mac.set_lben) {

			u32 pfdtxgswc;



			pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);

			pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;

			IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);

			hw->mac.set_lben = false;

		}

	}

}

drivers/net/ethernet/intel/ixgbe/ixgbe_common.h

+2 −0
Original line number Diff line number Diff line
@@ -130,6 +130,8 @@ void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, 


s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw);

s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw);

void ixgbe_disable_rx_generic(struct ixgbe_hw *hw);

void ixgbe_enable_rx_generic(struct ixgbe_hw *hw);



#define IXGBE_FAILED_READ_REG 0xffffffffU

#define IXGBE_FAILED_READ_CFG_DWORD 0xffffffffU