Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 315271b0 authored by Bjorn Helgaas's avatar Bjorn Helgaas Committed by Bjorn Helgaas
Browse files

Merge branch 'pci/enumeration' 

  - add decoding for 16 GT/s link speed (Jay Fang)

  - add interfaces to get max link speed and width (Tal Gilboa)

  - add pcie_bandwidth_capable() to compute max supported link bandwidth
    (Tal Gilboa)

  - add pcie_bandwidth_available() to compute bandwidth available to device
    (Tal Gilboa)

  - add pcie_print_link_status() to log link speed and whether it's limited
    (Tal Gilboa)

  - use PCI core interfaces to report when device performance may be
    limited by its slot instead of doing it in each driver (Tal Gilboa)

* pci/enumeration:
  fm10k: Report PCIe link properties with pcie_print_link_status()
  net/mlx5e: Use pcie_bandwidth_available() to compute bandwidth
  net/mlx5: Report PCIe link properties with pcie_print_link_status()
  net/mlx4_core: Report PCIe link properties with pcie_print_link_status()
  PCI: Add pcie_print_link_status() to log link speed and whether it's limited
  PCI: Add pcie_bandwidth_available() to compute bandwidth available to device
  PCI: Add pcie_bandwidth_capable() to compute max supported link bandwidth
  PCI: Add pcie_get_width_cap() to find max supported link width
  PCI: Add pcie_get_speed_cap() to find max supported link speed
  PCI: Add decoding for 16 GT/s link speed
parents db7a726e 170648fd

drivers/net/ethernet/intel/fm10k/fm10k_pci.c

+1 −86
Original line number Diff line number Diff line
@@ -2120,91 +2120,6 @@ static int fm10k_sw_init(struct fm10k_intfc *interface, 
	return 0;

}



static void fm10k_slot_warn(struct fm10k_intfc *interface)

{

	enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;

	enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;

	struct fm10k_hw *hw = &interface->hw;

	int max_gts = 0, expected_gts = 0;



	if (pcie_get_minimum_link(interface->pdev, &speed, &width) ||

	    speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {

		dev_warn(&interface->pdev->dev,

			 "Unable to determine PCI Express bandwidth.\n");

		return;

	}



	switch (speed) {

	case PCIE_SPEED_2_5GT:

		/* 8b/10b encoding reduces max throughput by 20% */

		max_gts = 2 * width;

		break;

	case PCIE_SPEED_5_0GT:

		/* 8b/10b encoding reduces max throughput by 20% */

		max_gts = 4 * width;

		break;

	case PCIE_SPEED_8_0GT:

		/* 128b/130b encoding has less than 2% impact on throughput */

		max_gts = 8 * width;

		break;

	default:

		dev_warn(&interface->pdev->dev,

			 "Unable to determine PCI Express bandwidth.\n");

		return;

	}



	dev_info(&interface->pdev->dev,

		 "PCI Express bandwidth of %dGT/s available\n",

		 max_gts);

	dev_info(&interface->pdev->dev,

		 "(Speed:%s, Width: x%d, Encoding Loss:%s, Payload:%s)\n",

		 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :

		  speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :

		  speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :

		  "Unknown"),

		 hw->bus.width,

		 (speed == PCIE_SPEED_2_5GT ? "20%" :

		  speed == PCIE_SPEED_5_0GT ? "20%" :

		  speed == PCIE_SPEED_8_0GT ? "<2%" :

		  "Unknown"),

		 (hw->bus.payload == fm10k_bus_payload_128 ? "128B" :

		  hw->bus.payload == fm10k_bus_payload_256 ? "256B" :

		  hw->bus.payload == fm10k_bus_payload_512 ? "512B" :

		  "Unknown"));



	switch (hw->bus_caps.speed) {

	case fm10k_bus_speed_2500:

		/* 8b/10b encoding reduces max throughput by 20% */

		expected_gts = 2 * hw->bus_caps.width;

		break;

	case fm10k_bus_speed_5000:

		/* 8b/10b encoding reduces max throughput by 20% */

		expected_gts = 4 * hw->bus_caps.width;

		break;

	case fm10k_bus_speed_8000:

		/* 128b/130b encoding has less than 2% impact on throughput */

		expected_gts = 8 * hw->bus_caps.width;

		break;

	default:

		dev_warn(&interface->pdev->dev,

			 "Unable to determine expected PCI Express bandwidth.\n");

		return;

	}



	if (max_gts >= expected_gts)

		return;



	dev_warn(&interface->pdev->dev,

		 "This device requires %dGT/s of bandwidth for optimal performance.\n",

		 expected_gts);

	dev_warn(&interface->pdev->dev,

		 "A %sslot with x%d lanes is suggested.\n",

		 (hw->bus_caps.speed == fm10k_bus_speed_2500 ? "2.5GT/s " :

		  hw->bus_caps.speed == fm10k_bus_speed_5000 ? "5.0GT/s " :

		  hw->bus_caps.speed == fm10k_bus_speed_8000 ? "8.0GT/s " : ""),

		 hw->bus_caps.width);

}



/**

 * fm10k_probe - Device Initialization Routine

 * @pdev: PCI device information struct
@@ -2326,7 +2241,7 @@ static int fm10k_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 
	mod_timer(&interface->service_timer, (HZ * 2) + jiffies);



	/* print warning for non-optimal configurations */

	fm10k_slot_warn(interface);

	pcie_print_link_status(interface->pdev);



	/* report MAC address for logging */

	dev_info(&pdev->dev, "%pM\n", netdev->dev_addr);

drivers/net/ethernet/mellanox/mlx4/main.c

+1 −80
Original line number Diff line number Diff line
@@ -623,85 +623,6 @@ static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 
	return 0;

}



static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,

				       enum pci_bus_speed *speed,

				       enum pcie_link_width *width)

{

	u32 lnkcap1, lnkcap2;

	int err1, err2;



#define  PCIE_MLW_CAP_SHIFT 4	/* start of MLW mask in link capabilities */



	*speed = PCI_SPEED_UNKNOWN;

	*width = PCIE_LNK_WIDTH_UNKNOWN;



	err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,

					  &lnkcap1);

	err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,

					  &lnkcap2);

	if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */

		if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)

			*speed = PCIE_SPEED_8_0GT;

		else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)

			*speed = PCIE_SPEED_5_0GT;

		else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)

			*speed = PCIE_SPEED_2_5GT;

	}

	if (!err1) {

		*width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;

		if (!lnkcap2) { /* pre-r3.0 */

			if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)

				*speed = PCIE_SPEED_5_0GT;

			else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)

				*speed = PCIE_SPEED_2_5GT;

		}

	}



	if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {

		return err1 ? err1 :

			err2 ? err2 : -EINVAL;

	}

	return 0;

}



static void mlx4_check_pcie_caps(struct mlx4_dev *dev)

{

	enum pcie_link_width width, width_cap;

	enum pci_bus_speed speed, speed_cap;

	int err;



#define PCIE_SPEED_STR(speed) \

	(speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \

	 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \

	 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \

	 "Unknown")



	err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);

	if (err) {

		mlx4_warn(dev,

			  "Unable to determine PCIe device BW capabilities\n");

		return;

	}



	err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);

	if (err || speed == PCI_SPEED_UNKNOWN ||

	    width == PCIE_LNK_WIDTH_UNKNOWN) {

		mlx4_warn(dev,

			  "Unable to determine PCI device chain minimum BW\n");

		return;

	}



	if (width != width_cap || speed != speed_cap)

		mlx4_warn(dev,

			  "PCIe BW is different than device's capability\n");



	mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",

		  PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));

	mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",

		  width, width_cap);

	return;

}



/*The function checks if there are live vf, return the num of them*/

static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)

{
@@ -3475,7 +3396,7 @@ static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data, 
	 * express device capabilities are under-satisfied by the bus.

	 */

	if (!mlx4_is_slave(dev))

		mlx4_check_pcie_caps(dev);

		pcie_print_link_status(dev->persist->pdev);



	/* In master functions, the communication channel must be initialized

	 * after obtaining its address from fw */

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

+1 −31
Original line number Diff line number Diff line
@@ -3864,36 +3864,6 @@ void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, 
		indirection_rqt[i] = i % num_channels;

}



static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)

{

	enum pcie_link_width width;

	enum pci_bus_speed speed;

	int err = 0;



	err = pcie_get_minimum_link(mdev->pdev, &speed, &width);

	if (err)

		return err;



	if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)

		return -EINVAL;



	switch (speed) {

	case PCIE_SPEED_2_5GT:

		*pci_bw = 2500 * width;

		break;

	case PCIE_SPEED_5_0GT:

		*pci_bw = 5000 * width;

		break;

	case PCIE_SPEED_8_0GT:

		*pci_bw = 8000 * width;

		break;

	default:

		return -EINVAL;

	}



	return 0;

}



static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)

{

	return (link_speed && pci_bw &&
@@ -3979,7 +3949,7 @@ void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, 
	params->num_tc       = 1;



	mlx5e_get_max_linkspeed(mdev, &link_speed);

	mlx5e_get_pci_bw(mdev, &pci_bw);

	pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);

	mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",

		      link_speed, pci_bw);

drivers/net/ethernet/mellanox/mlx5/core/main.c

+4 −0
Original line number Diff line number Diff line
@@ -1043,6 +1043,10 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 
	dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),

		 fw_rev_min(dev), fw_rev_sub(dev));



	/* Only PFs hold the relevant PCIe information for this query */

	if (mlx5_core_is_pf(dev))

		pcie_print_link_status(dev->pdev);



	/* on load removing any previous indication of internal error, device is

	 * up

	 */

drivers/pci/pci-sysfs.c

+7 −31
Original line number Diff line number Diff line
@@ -158,45 +158,18 @@ static DEVICE_ATTR_RO(resource); 
static ssize_t max_link_speed_show(struct device *dev,

				   struct device_attribute *attr, char *buf)

{

	struct pci_dev *pci_dev = to_pci_dev(dev);

	u32 linkcap;

	int err;

	const char *speed;



	err = pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &linkcap);

	if (err)

		return -EINVAL;



	switch (linkcap & PCI_EXP_LNKCAP_SLS) {

	case PCI_EXP_LNKCAP_SLS_8_0GB:

		speed = "8 GT/s";

		break;

	case PCI_EXP_LNKCAP_SLS_5_0GB:

		speed = "5 GT/s";

		break;

	case PCI_EXP_LNKCAP_SLS_2_5GB:

		speed = "2.5 GT/s";

		break;

	default:

		speed = "Unknown speed";

	}

	struct pci_dev *pdev = to_pci_dev(dev);



	return sprintf(buf, "%s\n", speed);

	return sprintf(buf, "%s\n", PCIE_SPEED2STR(pcie_get_speed_cap(pdev)));

}

static DEVICE_ATTR_RO(max_link_speed);



static ssize_t max_link_width_show(struct device *dev,

				   struct device_attribute *attr, char *buf)

{

	struct pci_dev *pci_dev = to_pci_dev(dev);

	u32 linkcap;

	int err;



	err = pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &linkcap);

	if (err)

		return -EINVAL;

	struct pci_dev *pdev = to_pci_dev(dev);



	return sprintf(buf, "%u\n", (linkcap & PCI_EXP_LNKCAP_MLW) >> 4);

	return sprintf(buf, "%u\n", pcie_get_width_cap(pdev));

}

static DEVICE_ATTR_RO(max_link_width);
@@ -213,6 +186,9 @@ static ssize_t current_link_speed_show(struct device *dev, 
		return -EINVAL;



	switch (linkstat & PCI_EXP_LNKSTA_CLS) {

	case PCI_EXP_LNKSTA_CLS_16_0GB:

		speed = "16 GT/s";

		break;

	case PCI_EXP_LNKSTA_CLS_8_0GB:

		speed = "8 GT/s";

		break;