Loading drivers/gpu/msm/adreno-gpulist.h +21 −0 Original line number Diff line number Diff line Loading @@ -953,6 +953,26 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619 = { .protected_regs = a630_protected_regs, }; static const struct adreno_a6xx_core adreno_gpu_core_a619_variant = { .base = { DEFINE_ADRENO_REV(ADRENO_REV_A619, 6, 1, 9, ANY_ID), .compatible = "qcom,adreno-gpu-a619-holi", .features = ADRENO_PREEMPTION | ADRENO_CONTENT_PROTECTION, .gpudev = &adreno_a6xx_gpudev, .gmem_size = SZ_512K, .bus_width = 32, }, .prim_fifo_threshold = 0x0018000, .sqefw_name = "a630_sqe.fw", .zap_name = "a615_zap", .hwcg = a615_hwcg_regs, .hwcg_count = ARRAY_SIZE(a615_hwcg_regs), .vbif = a615_gbif_regs, .vbif_count = ARRAY_SIZE(a615_gbif_regs), .hang_detect_cycles = 0x3fffff, .protected_regs = a630_protected_regs, }; static const struct adreno_reglist a620_hwcg_regs[] = { {A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, {A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, Loading Loading @@ -1574,6 +1594,7 @@ static const struct adreno_gpu_core *adreno_gpulist[] = { &adreno_gpu_core_a615.base, &adreno_gpu_core_a618.base, &adreno_gpu_core_a619.base, &adreno_gpu_core_a619_variant.base, &adreno_gpu_core_a620.base, &adreno_gpu_core_a640.base, &adreno_gpu_core_a650.base, Loading Loading
drivers/gpu/msm/adreno-gpulist.h +21 −0 Original line number Diff line number Diff line Loading @@ -953,6 +953,26 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619 = { .protected_regs = a630_protected_regs, }; static const struct adreno_a6xx_core adreno_gpu_core_a619_variant = { .base = { DEFINE_ADRENO_REV(ADRENO_REV_A619, 6, 1, 9, ANY_ID), .compatible = "qcom,adreno-gpu-a619-holi", .features = ADRENO_PREEMPTION | ADRENO_CONTENT_PROTECTION, .gpudev = &adreno_a6xx_gpudev, .gmem_size = SZ_512K, .bus_width = 32, }, .prim_fifo_threshold = 0x0018000, .sqefw_name = "a630_sqe.fw", .zap_name = "a615_zap", .hwcg = a615_hwcg_regs, .hwcg_count = ARRAY_SIZE(a615_hwcg_regs), .vbif = a615_gbif_regs, .vbif_count = ARRAY_SIZE(a615_gbif_regs), .hang_detect_cycles = 0x3fffff, .protected_regs = a630_protected_regs, }; static const struct adreno_reglist a620_hwcg_regs[] = { {A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, {A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, Loading Loading @@ -1574,6 +1594,7 @@ static const struct adreno_gpu_core *adreno_gpulist[] = { &adreno_gpu_core_a615.base, &adreno_gpu_core_a618.base, &adreno_gpu_core_a619.base, &adreno_gpu_core_a619_variant.base, &adreno_gpu_core_a620.base, &adreno_gpu_core_a640.base, &adreno_gpu_core_a650.base, Loading