[MIPS] Add CoreFPGA5 support; distinguish between SOCit/ROCit (30840244) · Commits · e / devices / android_kernel_fairphone_FP5

arch/mips/mips-boards/generic/init.c

+11 −5

Original line number	Original line	Diff line number	Diff line
	@@ -295,15 +295,21 @@ void __init prom_init(void)
	break;		break;
	case MIPS_REVISION_CORID_CORE_MSC:		case MIPS_REVISION_CORID_CORE_MSC:
	case MIPS_REVISION_CORID_CORE_FPGA2:		case MIPS_REVISION_CORID_CORE_FPGA2:
	case MIPS_REVISION_CORID_CORE_FPGA3:
	case MIPS_REVISION_CORID_CORE_FPGA4:
	case MIPS_REVISION_CORID_CORE_24K:		case MIPS_REVISION_CORID_CORE_24K:
	case MIPS_REVISION_CORID_CORE_EMUL_MSC:		/*
			* SOCit/ROCit support is essentially identical
			* but make an attempt to distinguish them
			*/
	mips_revision_sconid = MIPS_REVISION_SCON_SOCIT;		mips_revision_sconid = MIPS_REVISION_SCON_SOCIT;
	break;		break;
			case MIPS_REVISION_CORID_CORE_FPGA3:
			case MIPS_REVISION_CORID_CORE_FPGA4:
			case MIPS_REVISION_CORID_CORE_FPGA5:
			case MIPS_REVISION_CORID_CORE_EMUL_MSC:
	default:		default:
	mips_display_message("CC Error");		/* See above */
	while (1); /* We die here... */		mips_revision_sconid = MIPS_REVISION_SCON_ROCIT;
			break;
	}		}
	}		}

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -68,6 +68,7 @@
	#define MIPS_REVISION_CORID_CORE_FPGA3 9		#define MIPS_REVISION_CORID_CORE_FPGA3 9
	#define MIPS_REVISION_CORID_CORE_24K 10		#define MIPS_REVISION_CORID_CORE_24K 10
	#define MIPS_REVISION_CORID_CORE_FPGA4 11		#define MIPS_REVISION_CORID_CORE_FPGA4 11
			#define MIPS_REVISION_CORID_CORE_FPGA5 12

	/** Artificial corid defines **/		/** Artificial corid defines **/
	/*		/*