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Commit 3051719a authored by Eric Anholt's avatar Eric Anholt
Browse files

drm/vc4: Use drm_print_regset32() for our debug register dumping. 



This removes a bunch of duplicated boilerplate for the debugfs vs
runtime printk debug dumping.

Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20190220210343.28157-2-eric@anholt.net


Reviewed-by: default avatarPaul Kocialkowski <paul.kocialkowski@bootlin.com>
parent 5f513cc8

drivers/gpu/drm/vc4/vc4_crtc.c

+30 −38
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
#include <drm/drm_atomic.h>

#include <drm/drm_atomic_helper.h>

#include <drm/drm_atomic_uapi.h>

#include <drm/drm_print.h>

#include <drm/drm_probe_helper.h>

#include <linux/clk.h>

#include <drm/drm_fb_cma_helper.h>
@@ -67,43 +68,29 @@ to_vc4_crtc_state(struct drm_crtc_state *crtc_state) 
#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))

#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))



#define CRTC_REG(reg) { reg, #reg }

static const struct {

	u32 reg;

	const char *name;

} crtc_regs[] = {

	CRTC_REG(PV_CONTROL),

	CRTC_REG(PV_V_CONTROL),

	CRTC_REG(PV_VSYNCD_EVEN),

	CRTC_REG(PV_HORZA),

	CRTC_REG(PV_HORZB),

	CRTC_REG(PV_VERTA),

	CRTC_REG(PV_VERTB),

	CRTC_REG(PV_VERTA_EVEN),

	CRTC_REG(PV_VERTB_EVEN),

	CRTC_REG(PV_INTEN),

	CRTC_REG(PV_INTSTAT),

	CRTC_REG(PV_STAT),

	CRTC_REG(PV_HACT_ACT),

static const struct debugfs_reg32 crtc_regs[] = {

	VC4_REG32(PV_CONTROL),

	VC4_REG32(PV_V_CONTROL),

	VC4_REG32(PV_VSYNCD_EVEN),

	VC4_REG32(PV_HORZA),

	VC4_REG32(PV_HORZB),

	VC4_REG32(PV_VERTA),

	VC4_REG32(PV_VERTB),

	VC4_REG32(PV_VERTA_EVEN),

	VC4_REG32(PV_VERTB_EVEN),

	VC4_REG32(PV_INTEN),

	VC4_REG32(PV_INTSTAT),

	VC4_REG32(PV_STAT),

	VC4_REG32(PV_HACT_ACT),

};



static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)

{

	int i;



	for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {

		DRM_INFO("0x%04x (%s): 0x%08x\n",

			 crtc_regs[i].reg, crtc_regs[i].name,

			 CRTC_READ(crtc_regs[i].reg));

	}

}



#ifdef CONFIG_DEBUG_FS

int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = (struct drm_info_node *)m->private;

	struct drm_device *dev = node->minor->dev;

	int crtc_index = (uintptr_t)node->info_ent->data;

	struct drm_printer p = drm_seq_file_printer(m);

	struct drm_crtc *crtc;

	struct vc4_crtc *vc4_crtc;

	int i;
@@ -118,11 +105,7 @@ int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused) 
		return 0;

	vc4_crtc = to_vc4_crtc(crtc);



	for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {

		seq_printf(m, "%s (0x%04x): 0x%08x\n",

			   crtc_regs[i].name, crtc_regs[i].reg,

			   CRTC_READ(crtc_regs[i].reg));

	}

	drm_print_regset32(&p, &vc4_crtc->regset);



	return 0;

}
@@ -434,8 +417,10 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) 
	bool debug_dump_regs = false;



	if (debug_dump_regs) {

		DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));

		vc4_crtc_dump_regs(vc4_crtc);

		struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);

		dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",

			 drm_crtc_index(crtc));

		drm_print_regset32(&p, &vc4_crtc->regset);

	}



	if (vc4_crtc->channel == 2) {
@@ -476,8 +461,10 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) 
	vc4_crtc_lut_load(crtc);



	if (debug_dump_regs) {

		DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));

		vc4_crtc_dump_regs(vc4_crtc);

		struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);

		dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",

			 drm_crtc_index(crtc));

		drm_print_regset32(&p, &vc4_crtc->regset);

	}

}
@@ -1177,11 +1164,16 @@ static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) 
	if (!match)

		return -ENODEV;

	vc4_crtc->data = match->data;

	vc4_crtc->pdev = pdev;



	vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);

	if (IS_ERR(vc4_crtc->regs))

		return PTR_ERR(vc4_crtc->regs);



	vc4_crtc->regset.base = vc4_crtc->regs;

	vc4_crtc->regset.regs = crtc_regs;

	vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);



	/* For now, we create just the primary and the legacy cursor

	 * planes.  We should be able to stack more planes on easily,

	 * but to do that we would need to compute the bandwidth

drivers/gpu/drm/vc4/vc4_dpi.c

+10 −13
Original line number Diff line number Diff line
@@ -101,6 +101,8 @@ struct vc4_dpi { 


	struct clk *pixel_clock;

	struct clk *core_clock;



	struct debugfs_regset32 regset;

};



#define DPI_READ(offset) readl(dpi->regs + (offset))
@@ -118,13 +120,9 @@ to_vc4_dpi_encoder(struct drm_encoder *encoder) 
	return container_of(encoder, struct vc4_dpi_encoder, base.base);

}



#define DPI_REG(reg) { reg, #reg }

static const struct {

	u32 reg;

	const char *name;

} dpi_regs[] = {

	DPI_REG(DPI_C),

	DPI_REG(DPI_ID),

static const struct debugfs_reg32 dpi_regs[] = {

	VC4_REG32(DPI_C),

	VC4_REG32(DPI_ID),

};



#ifdef CONFIG_DEBUG_FS
@@ -134,16 +132,12 @@ int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused) 
	struct drm_device *dev = node->minor->dev;

	struct vc4_dev *vc4 = to_vc4_dev(dev);

	struct vc4_dpi *dpi = vc4->dpi;

	int i;

	struct drm_printer p = drm_seq_file_printer(m);



	if (!dpi)

		return 0;



	for (i = 0; i < ARRAY_SIZE(dpi_regs); i++) {

		seq_printf(m, "%s (0x%04x): 0x%08x\n",

			   dpi_regs[i].name, dpi_regs[i].reg,

			   DPI_READ(dpi_regs[i].reg));

	}

	drm_print_regset32(&p, &dpi->regset);



	return 0;

}
@@ -314,6 +308,9 @@ static int vc4_dpi_bind(struct device *dev, struct device *master, void *data) 
	dpi->regs = vc4_ioremap_regs(pdev, 0);

	if (IS_ERR(dpi->regs))

		return PTR_ERR(dpi->regs);

	dpi->regset.base = dpi->regs;

	dpi->regset.regs = dpi_regs;

	dpi->regset.nregs = ARRAY_SIZE(dpi_regs);



	if (DPI_READ(DPI_ID) != DPI_ID_VALUE) {

		dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n",

drivers/gpu/drm/vc4/vc4_drv.h

+7 −0
Original line number Diff line number Diff line
@@ -296,6 +296,7 @@ struct vc4_v3d { 
	struct platform_device *pdev;

	void __iomem *regs;

	struct clk *clk;

	struct debugfs_regset32 regset;

};



struct vc4_hvs {
@@ -312,6 +313,7 @@ struct vc4_hvs { 
	spinlock_t mm_lock;



	struct drm_mm_node mitchell_netravali_filter;

	struct debugfs_regset32 regset;

};



struct vc4_plane {
@@ -431,6 +433,7 @@ struct vc4_crtc_data { 


struct vc4_crtc {

	struct drm_crtc base;

	struct platform_device *pdev;

	const struct vc4_crtc_data *data;

	void __iomem *regs;
@@ -447,6 +450,8 @@ struct vc4_crtc { 
	u32 cob_size;



	struct drm_pending_vblank_event *event;



	struct debugfs_regset32 regset;

};



static inline struct vc4_crtc *
@@ -460,6 +465,8 @@ to_vc4_crtc(struct drm_crtc *crtc) 
#define HVS_READ(offset) readl(vc4->hvs->regs + offset)

#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)



#define VC4_REG32(reg) { .name = #reg, .offset = reg }



struct vc4_exec_info {

	/* Sequence number for this bin/render job. */

	uint64_t seqno;

drivers/gpu/drm/vc4/vc4_dsi.c

+65 −90
Original line number Diff line number Diff line
@@ -545,6 +545,8 @@ struct vc4_dsi { 


	struct completion xfer_completion;

	int xfer_result;



	struct debugfs_regset32 regset;

};



#define host_to_dsi(host) container_of(host, struct vc4_dsi, dsi_host)
@@ -605,82 +607,56 @@ to_vc4_dsi_encoder(struct drm_encoder *encoder) 
	return container_of(encoder, struct vc4_dsi_encoder, base.base);

}



#define DSI_REG(reg) { reg, #reg }

static const struct {

	u32 reg;

	const char *name;

} dsi0_regs[] = {

	DSI_REG(DSI0_CTRL),

	DSI_REG(DSI0_STAT),

	DSI_REG(DSI0_HSTX_TO_CNT),

	DSI_REG(DSI0_LPRX_TO_CNT),

	DSI_REG(DSI0_TA_TO_CNT),

	DSI_REG(DSI0_PR_TO_CNT),

	DSI_REG(DSI0_DISP0_CTRL),

	DSI_REG(DSI0_DISP1_CTRL),

	DSI_REG(DSI0_INT_STAT),

	DSI_REG(DSI0_INT_EN),

	DSI_REG(DSI0_PHYC),

	DSI_REG(DSI0_HS_CLT0),

	DSI_REG(DSI0_HS_CLT1),

	DSI_REG(DSI0_HS_CLT2),

	DSI_REG(DSI0_HS_DLT3),

	DSI_REG(DSI0_HS_DLT4),

	DSI_REG(DSI0_HS_DLT5),

	DSI_REG(DSI0_HS_DLT6),

	DSI_REG(DSI0_HS_DLT7),

	DSI_REG(DSI0_PHY_AFEC0),

	DSI_REG(DSI0_PHY_AFEC1),

	DSI_REG(DSI0_ID),

static const struct debugfs_reg32 dsi0_regs[] = {

	VC4_REG32(DSI0_CTRL),

	VC4_REG32(DSI0_STAT),

	VC4_REG32(DSI0_HSTX_TO_CNT),

	VC4_REG32(DSI0_LPRX_TO_CNT),

	VC4_REG32(DSI0_TA_TO_CNT),

	VC4_REG32(DSI0_PR_TO_CNT),

	VC4_REG32(DSI0_DISP0_CTRL),

	VC4_REG32(DSI0_DISP1_CTRL),

	VC4_REG32(DSI0_INT_STAT),

	VC4_REG32(DSI0_INT_EN),

	VC4_REG32(DSI0_PHYC),

	VC4_REG32(DSI0_HS_CLT0),

	VC4_REG32(DSI0_HS_CLT1),

	VC4_REG32(DSI0_HS_CLT2),

	VC4_REG32(DSI0_HS_DLT3),

	VC4_REG32(DSI0_HS_DLT4),

	VC4_REG32(DSI0_HS_DLT5),

	VC4_REG32(DSI0_HS_DLT6),

	VC4_REG32(DSI0_HS_DLT7),

	VC4_REG32(DSI0_PHY_AFEC0),

	VC4_REG32(DSI0_PHY_AFEC1),

	VC4_REG32(DSI0_ID),

};



static const struct {

	u32 reg;

	const char *name;

} dsi1_regs[] = {

	DSI_REG(DSI1_CTRL),

	DSI_REG(DSI1_STAT),

	DSI_REG(DSI1_HSTX_TO_CNT),

	DSI_REG(DSI1_LPRX_TO_CNT),

	DSI_REG(DSI1_TA_TO_CNT),

	DSI_REG(DSI1_PR_TO_CNT),

	DSI_REG(DSI1_DISP0_CTRL),

	DSI_REG(DSI1_DISP1_CTRL),

	DSI_REG(DSI1_INT_STAT),

	DSI_REG(DSI1_INT_EN),

	DSI_REG(DSI1_PHYC),

	DSI_REG(DSI1_HS_CLT0),

	DSI_REG(DSI1_HS_CLT1),

	DSI_REG(DSI1_HS_CLT2),

	DSI_REG(DSI1_HS_DLT3),

	DSI_REG(DSI1_HS_DLT4),

	DSI_REG(DSI1_HS_DLT5),

	DSI_REG(DSI1_HS_DLT6),

	DSI_REG(DSI1_HS_DLT7),

	DSI_REG(DSI1_PHY_AFEC0),

	DSI_REG(DSI1_PHY_AFEC1),

	DSI_REG(DSI1_ID),

static const struct debugfs_reg32 dsi1_regs[] = {

	VC4_REG32(DSI1_CTRL),

	VC4_REG32(DSI1_STAT),

	VC4_REG32(DSI1_HSTX_TO_CNT),

	VC4_REG32(DSI1_LPRX_TO_CNT),

	VC4_REG32(DSI1_TA_TO_CNT),

	VC4_REG32(DSI1_PR_TO_CNT),

	VC4_REG32(DSI1_DISP0_CTRL),

	VC4_REG32(DSI1_DISP1_CTRL),

	VC4_REG32(DSI1_INT_STAT),

	VC4_REG32(DSI1_INT_EN),

	VC4_REG32(DSI1_PHYC),

	VC4_REG32(DSI1_HS_CLT0),

	VC4_REG32(DSI1_HS_CLT1),

	VC4_REG32(DSI1_HS_CLT2),

	VC4_REG32(DSI1_HS_DLT3),

	VC4_REG32(DSI1_HS_DLT4),

	VC4_REG32(DSI1_HS_DLT5),

	VC4_REG32(DSI1_HS_DLT6),

	VC4_REG32(DSI1_HS_DLT7),

	VC4_REG32(DSI1_PHY_AFEC0),

	VC4_REG32(DSI1_PHY_AFEC1),

	VC4_REG32(DSI1_ID),

};



static void vc4_dsi_dump_regs(struct vc4_dsi *dsi)

{

	int i;



	if (dsi->port == 0) {

		for (i = 0; i < ARRAY_SIZE(dsi0_regs); i++) {

			DRM_INFO("0x%04x (%s): 0x%08x\n",

				 dsi0_regs[i].reg, dsi0_regs[i].name,

				 DSI_READ(dsi0_regs[i].reg));

		}

	} else {

		for (i = 0; i < ARRAY_SIZE(dsi1_regs); i++) {

			DRM_INFO("0x%04x (%s): 0x%08x\n",

				 dsi1_regs[i].reg, dsi1_regs[i].name,

				 DSI_READ(dsi1_regs[i].reg));

		}

	}

}



#ifdef CONFIG_DEBUG_FS

int vc4_dsi_debugfs_regs(struct seq_file *m, void *unused)

{
@@ -689,24 +665,12 @@ int vc4_dsi_debugfs_regs(struct seq_file *m, void *unused) 
	struct vc4_dev *vc4 = to_vc4_dev(drm);

	int dsi_index = (uintptr_t)node->info_ent->data;

	struct vc4_dsi *dsi = (dsi_index == 1 ? vc4->dsi1 : NULL);

	int i;

	struct drm_printer p = drm_seq_file_printer(m);



	if (!dsi)

		return 0;



	if (dsi->port == 0) {

		for (i = 0; i < ARRAY_SIZE(dsi0_regs); i++) {

			seq_printf(m, "0x%04x (%s): 0x%08x\n",

				   dsi0_regs[i].reg, dsi0_regs[i].name,

				   DSI_READ(dsi0_regs[i].reg));

		}

	} else {

		for (i = 0; i < ARRAY_SIZE(dsi1_regs); i++) {

			seq_printf(m, "0x%04x (%s): 0x%08x\n",

				   dsi1_regs[i].reg, dsi1_regs[i].name,

				   DSI_READ(dsi1_regs[i].reg));

		}

	}

	drm_print_regset32(&p, &dsi->regset);



	return 0;

}
@@ -900,8 +864,9 @@ static void vc4_dsi_encoder_enable(struct drm_encoder *encoder) 
	}



	if (debug_dump_regs) {

		DRM_INFO("DSI regs before:\n");

		vc4_dsi_dump_regs(dsi);

		struct drm_printer p = drm_info_printer(&dsi->pdev->dev);

		dev_info(&dsi->pdev->dev, "DSI regs before:\n");

		drm_print_regset32(&p, &dsi->regset);

	}



	/* Round up the clk_set_rate() request slightly, since
@@ -1135,8 +1100,9 @@ static void vc4_dsi_encoder_enable(struct drm_encoder *encoder) 
	drm_bridge_enable(dsi->bridge);



	if (debug_dump_regs) {

		DRM_INFO("DSI regs after:\n");

		vc4_dsi_dump_regs(dsi);

		struct drm_printer p = drm_info_printer(&dsi->pdev->dev);

		dev_info(&dsi->pdev->dev, "DSI regs after:\n");

		drm_print_regset32(&p, &dsi->regset);

	}

}
@@ -1527,6 +1493,15 @@ static int vc4_dsi_bind(struct device *dev, struct device *master, void *data) 
	if (IS_ERR(dsi->regs))

		return PTR_ERR(dsi->regs);



	dsi->regset.base = dsi->regs;

	if (dsi->port == 0) {

		dsi->regset.regs = dsi0_regs;

		dsi->regset.nregs = ARRAY_SIZE(dsi0_regs);

	} else {

		dsi->regset.regs = dsi1_regs;

		dsi->regset.nregs = ARRAY_SIZE(dsi1_regs);

	}



	if (DSI_PORT_READ(ID) != DSI_ID_VALUE) {

		dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n",

			DSI_PORT_READ(ID), DSI_ID_VALUE);

drivers/gpu/drm/vc4/vc4_hdmi.c

+70 −86
Original line number Diff line number Diff line
@@ -97,6 +97,9 @@ struct vc4_hdmi { 


	struct clk *pixel_clock;

	struct clk *hsm_clock;



	struct debugfs_regset32 hdmi_regset;

	struct debugfs_regset32 hd_regset;

};



#define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
@@ -134,61 +137,54 @@ to_vc4_hdmi_connector(struct drm_connector *connector) 
	return container_of(connector, struct vc4_hdmi_connector, base);

}



#define HDMI_REG(reg) { reg, #reg }

static const struct {

	u32 reg;

	const char *name;

} hdmi_regs[] = {

	HDMI_REG(VC4_HDMI_CORE_REV),

	HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),

	HDMI_REG(VC4_HDMI_HOTPLUG_INT),

	HDMI_REG(VC4_HDMI_HOTPLUG),

	HDMI_REG(VC4_HDMI_MAI_CHANNEL_MAP),

	HDMI_REG(VC4_HDMI_MAI_CONFIG),

	HDMI_REG(VC4_HDMI_MAI_FORMAT),

	HDMI_REG(VC4_HDMI_AUDIO_PACKET_CONFIG),

	HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),

	HDMI_REG(VC4_HDMI_HORZA),

	HDMI_REG(VC4_HDMI_HORZB),

	HDMI_REG(VC4_HDMI_FIFO_CTL),

	HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL),

	HDMI_REG(VC4_HDMI_VERTA0),

	HDMI_REG(VC4_HDMI_VERTA1),

	HDMI_REG(VC4_HDMI_VERTB0),

	HDMI_REG(VC4_HDMI_VERTB1),

	HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL),

	HDMI_REG(VC4_HDMI_TX_PHY_CTL0),



	HDMI_REG(VC4_HDMI_CEC_CNTRL_1),

	HDMI_REG(VC4_HDMI_CEC_CNTRL_2),

	HDMI_REG(VC4_HDMI_CEC_CNTRL_3),

	HDMI_REG(VC4_HDMI_CEC_CNTRL_4),

	HDMI_REG(VC4_HDMI_CEC_CNTRL_5),

	HDMI_REG(VC4_HDMI_CPU_STATUS),

	HDMI_REG(VC4_HDMI_CPU_MASK_STATUS),



	HDMI_REG(VC4_HDMI_CEC_RX_DATA_1),

	HDMI_REG(VC4_HDMI_CEC_RX_DATA_2),

	HDMI_REG(VC4_HDMI_CEC_RX_DATA_3),

	HDMI_REG(VC4_HDMI_CEC_RX_DATA_4),

	HDMI_REG(VC4_HDMI_CEC_TX_DATA_1),

	HDMI_REG(VC4_HDMI_CEC_TX_DATA_2),

	HDMI_REG(VC4_HDMI_CEC_TX_DATA_3),

	HDMI_REG(VC4_HDMI_CEC_TX_DATA_4),

static const struct debugfs_reg32 hdmi_regs[] = {

	VC4_REG32(VC4_HDMI_CORE_REV),

	VC4_REG32(VC4_HDMI_SW_RESET_CONTROL),

	VC4_REG32(VC4_HDMI_HOTPLUG_INT),

	VC4_REG32(VC4_HDMI_HOTPLUG),

	VC4_REG32(VC4_HDMI_MAI_CHANNEL_MAP),

	VC4_REG32(VC4_HDMI_MAI_CONFIG),

	VC4_REG32(VC4_HDMI_MAI_FORMAT),

	VC4_REG32(VC4_HDMI_AUDIO_PACKET_CONFIG),

	VC4_REG32(VC4_HDMI_RAM_PACKET_CONFIG),

	VC4_REG32(VC4_HDMI_HORZA),

	VC4_REG32(VC4_HDMI_HORZB),

	VC4_REG32(VC4_HDMI_FIFO_CTL),

	VC4_REG32(VC4_HDMI_SCHEDULER_CONTROL),

	VC4_REG32(VC4_HDMI_VERTA0),

	VC4_REG32(VC4_HDMI_VERTA1),

	VC4_REG32(VC4_HDMI_VERTB0),

	VC4_REG32(VC4_HDMI_VERTB1),

	VC4_REG32(VC4_HDMI_TX_PHY_RESET_CTL),

	VC4_REG32(VC4_HDMI_TX_PHY_CTL0),



	VC4_REG32(VC4_HDMI_CEC_CNTRL_1),

	VC4_REG32(VC4_HDMI_CEC_CNTRL_2),

	VC4_REG32(VC4_HDMI_CEC_CNTRL_3),

	VC4_REG32(VC4_HDMI_CEC_CNTRL_4),

	VC4_REG32(VC4_HDMI_CEC_CNTRL_5),

	VC4_REG32(VC4_HDMI_CPU_STATUS),

	VC4_REG32(VC4_HDMI_CPU_MASK_STATUS),



	VC4_REG32(VC4_HDMI_CEC_RX_DATA_1),

	VC4_REG32(VC4_HDMI_CEC_RX_DATA_2),

	VC4_REG32(VC4_HDMI_CEC_RX_DATA_3),

	VC4_REG32(VC4_HDMI_CEC_RX_DATA_4),

	VC4_REG32(VC4_HDMI_CEC_TX_DATA_1),

	VC4_REG32(VC4_HDMI_CEC_TX_DATA_2),

	VC4_REG32(VC4_HDMI_CEC_TX_DATA_3),

	VC4_REG32(VC4_HDMI_CEC_TX_DATA_4),

};



static const struct {

	u32 reg;

	const char *name;

} hd_regs[] = {

	HDMI_REG(VC4_HD_M_CTL),

	HDMI_REG(VC4_HD_MAI_CTL),

	HDMI_REG(VC4_HD_MAI_THR),

	HDMI_REG(VC4_HD_MAI_FMT),

	HDMI_REG(VC4_HD_MAI_SMP),

	HDMI_REG(VC4_HD_VID_CTL),

	HDMI_REG(VC4_HD_CSC_CTL),

	HDMI_REG(VC4_HD_FRAME_COUNT),

static const struct debugfs_reg32 hd_regs[] = {

	VC4_REG32(VC4_HD_M_CTL),

	VC4_REG32(VC4_HD_MAI_CTL),

	VC4_REG32(VC4_HD_MAI_THR),

	VC4_REG32(VC4_HD_MAI_FMT),

	VC4_REG32(VC4_HD_MAI_SMP),

	VC4_REG32(VC4_HD_VID_CTL),

	VC4_REG32(VC4_HD_CSC_CTL),

	VC4_REG32(VC4_HD_FRAME_COUNT),

};



#ifdef CONFIG_DEBUG_FS
@@ -197,41 +193,16 @@ int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 
	struct drm_info_node *node = (struct drm_info_node *)m->private;

	struct drm_device *dev = node->minor->dev;

	struct vc4_dev *vc4 = to_vc4_dev(dev);

	int i;



	for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {

		seq_printf(m, "%s (0x%04x): 0x%08x\n",

			   hdmi_regs[i].name, hdmi_regs[i].reg,

			   HDMI_READ(hdmi_regs[i].reg));

	}

	struct vc4_hdmi *hdmi = vc4->hdmi;

	struct drm_printer p = drm_seq_file_printer(m);



	for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {

		seq_printf(m, "%s (0x%04x): 0x%08x\n",

			   hd_regs[i].name, hd_regs[i].reg,

			   HD_READ(hd_regs[i].reg));

	}

	drm_print_regset32(&p, &hdmi->hdmi_regset);

	drm_print_regset32(&p, &hdmi->hd_regset);



	return 0;

}

#endif /* CONFIG_DEBUG_FS */



static void vc4_hdmi_dump_regs(struct drm_device *dev)

{

	struct vc4_dev *vc4 = to_vc4_dev(dev);

	int i;



	for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {

		DRM_INFO("0x%04x (%s): 0x%08x\n",

			 hdmi_regs[i].reg, hdmi_regs[i].name,

			 HDMI_READ(hdmi_regs[i].reg));

	}

	for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {

		DRM_INFO("0x%04x (%s): 0x%08x\n",

			 hd_regs[i].reg, hd_regs[i].name,

			 HD_READ(hd_regs[i].reg));

	}

}



static enum drm_connector_status

vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)

{
@@ -561,8 +532,11 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 
	HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);



	if (debug_dump_regs) {

		DRM_INFO("HDMI regs before:\n");

		vc4_hdmi_dump_regs(dev);

		struct drm_printer p = drm_info_printer(&hdmi->pdev->dev);



		dev_info(&hdmi->pdev->dev, "HDMI regs before:\n");

		drm_print_regset32(&p, &hdmi->hdmi_regset);

		drm_print_regset32(&p, &hdmi->hd_regset);

	}



	HD_WRITE(VC4_HD_VID_CTL, 0);
@@ -637,8 +611,11 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 
	HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);



	if (debug_dump_regs) {

		DRM_INFO("HDMI regs after:\n");

		vc4_hdmi_dump_regs(dev);

		struct drm_printer p = drm_info_printer(&hdmi->pdev->dev);



		dev_info(&hdmi->pdev->dev, "HDMI regs after:\n");

		drm_print_regset32(&p, &hdmi->hdmi_regset);

		drm_print_regset32(&p, &hdmi->hd_regset);

	}



	HD_WRITE(VC4_HD_VID_CTL,
@@ -1333,6 +1310,13 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 
	if (IS_ERR(hdmi->hd_regs))

		return PTR_ERR(hdmi->hd_regs);



	hdmi->hdmi_regset.base = hdmi->hdmicore_regs;

	hdmi->hdmi_regset.regs = hdmi_regs;

	hdmi->hdmi_regset.nregs = ARRAY_SIZE(hdmi_regs);

	hdmi->hd_regset.base = hdmi->hd_regs;

	hdmi->hd_regset.regs = hd_regs;

	hdmi->hd_regset.nregs = ARRAY_SIZE(hd_regs);



	hdmi->pixel_clock = devm_clk_get(dev, "pixel");

	if (IS_ERR(hdmi->pixel_clock)) {

		DRM_ERROR("Failed to get pixel clock\n");