Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3045f94a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-ras-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 RAS update from Ingo Molnar:
 "The changes in this tree are:

   - ACPI APEI (ACPI Platform Error Interface) improvements, by Chen
     Gong
   - misc MCE fixes/cleanups"

* 'x86-ras-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/mce: Update MCE severity condition check
  mce: acpi/apei: Add comments to clarify usage of the various bitfields in the MCA subsystem
  ACPI/APEI: Update einj documentation for param1/param2
  ACPI/APEI: Add parameter check before error injection
  ACPI, APEI, EINJ: Fix error return code in einj_init()
  x86, mce: Fix "braodcast" typo
parents 52e8ad90 fb476cff

Documentation/acpi/apei/einj.txt

+7 −2
Original line number Diff line number Diff line
@@ -47,11 +47,16 @@ directory apei/einj. The following files are provided. 


- param1

  This file is used to set the first error parameter value. Effect of

  parameter depends on error_type specified.

  parameter depends on error_type specified. For example, if error

  type is memory related type, the param1 should be a valid physical

  memory address.



- param2

  This file is used to set the second error parameter value. Effect of

  parameter depends on error_type specified.

  parameter depends on error_type specified. For example, if error

  type is memory related type, the param2 should be a physical memory

  address mask. Linux requires page or narrower granularity, say,

  0xfffffffffffff000.



- notrigger

  The EINJ mechanism is a two step process. First inject the error, then

arch/x86/include/asm/mce.h

+1 −1
Original line number Diff line number Diff line
@@ -61,7 +61,7 @@ 
#define MCJ_CTX_IRQ		0x2  /* inject context: IRQ */

#define MCJ_NMI_BROADCAST	0x4  /* do NMI broadcasting */

#define MCJ_EXCEPTION		0x8  /* raise as exception */

#define MCJ_IRQ_BRAODCAST	0x10 /* do IRQ broadcasting */

#define MCJ_IRQ_BROADCAST	0x10 /* do IRQ broadcasting */



#define MCE_OVERFLOW 0		/* bit 0 in flags means overflow */

arch/x86/kernel/cpu/mcheck/mce-inject.c

+2 −2
Original line number Diff line number Diff line
@@ -153,7 +153,7 @@ static void raise_mce(struct mce *m) 
		return;



#ifdef CONFIG_X86_LOCAL_APIC

	if (m->inject_flags & (MCJ_IRQ_BRAODCAST | MCJ_NMI_BROADCAST)) {

	if (m->inject_flags & (MCJ_IRQ_BROADCAST | MCJ_NMI_BROADCAST)) {

		unsigned long start;

		int cpu;
@@ -167,7 +167,7 @@ static void raise_mce(struct mce *m) 
				cpumask_clear_cpu(cpu, mce_inject_cpumask);

		}

		if (!cpumask_empty(mce_inject_cpumask)) {

			if (m->inject_flags & MCJ_IRQ_BRAODCAST) {

			if (m->inject_flags & MCJ_IRQ_BROADCAST) {

				/*

				 * don't wait because mce_irq_ipi is necessary

				 * to be sync with following raise_local

arch/x86/kernel/cpu/mcheck/mce-severity.c

+5 −10
Original line number Diff line number Diff line
@@ -110,22 +110,17 @@ static struct severity { 
	/* known AR MCACODs: */

#ifdef	CONFIG_MEMORY_FAILURE

	MCESEV(

		KEEP, "HT thread notices Action required: data load error",

		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),

		MCGMASK(MCG_STATUS_EIPV, 0)

		KEEP, "Action required but unaffected thread is continuable",

		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR),

		MCGMASK(MCG_STATUS_RIPV, MCG_STATUS_RIPV)

		),

	MCESEV(

		AR, "Action required: data load error",

		AR, "Action required: data load error in a user process",

		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),

		USER

		),

	MCESEV(

		KEEP, "HT thread notices Action required: instruction fetch error",

		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),

		MCGMASK(MCG_STATUS_EIPV, 0)

		),

	MCESEV(

		AR, "Action required: instruction fetch error",

		AR, "Action required: instruction fetch error in a user process",

		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),

		USER

		),

arch/x86/kernel/cpu/mcheck/mce.c

+4 −1
Original line number Diff line number Diff line
@@ -89,7 +89,10 @@ static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); 
static DEFINE_PER_CPU(struct mce, mces_seen);

static int			cpu_missing;



/* MCA banks polled by the period polling timer for corrected events */

/*

 * MCA banks polled by the period polling timer for corrected events.

 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).

 */

DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {

	[0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL

};