Merge "msm: kgsl: Replace the sorted dispatcher pending list" (3045517e) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/gpu/msm/adreno-gpulist.h

+38 −0

Original line number	Diff line number	Diff line
		@@ -30,6 +30,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306 = {
		.gmem_size = SZ_128K,
		.busy_mask = 0x7ffffffe,
		.bus_width = 0,
		.snapshot_size = 600 * SZ_1K,
		},
		.pm4fw_name = "a300_pm4.fw",
		.pfpfw_name = "a300_pfp.fw",
		@@ -52,6 +53,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306a = {
		.gmem_size = SZ_128K,
		.busy_mask = 0x7ffffffe,
		.bus_width = 16,
		.snapshot_size = 600 * SZ_1K,
		},
		.pm4fw_name = "a300_pm4.fw",
		.pfpfw_name = "a300_pfp.fw",
		@@ -72,6 +74,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a304 = {
		.gmem_size = (SZ_64K + SZ_32K),
		.busy_mask = 0x7ffffffe,
		.bus_width = 0,
		.snapshot_size = 600 * SZ_1K,
		},
		.pm4fw_name = "a300_pm4.fw",
		.pfpfw_name = "a300_pfp.fw",
		@@ -196,6 +199,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v2 = {
		.gmem_size = SZ_1M,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		.snapshot_size = SZ_1M,
		},
		.gpmu_tsens = 0x00060007,
		.max_power = 5448,
		@@ -208,6 +212,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v2 = {
		.hwcg_count = ARRAY_SIZE(a530_hwcg_regs),
		.vbif = a530_vbif_regs,
		.vbif_count = ARRAY_SIZE(a530_vbif_regs),
		.highest_bank_bit = 15,
		};

		static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = {
		@@ -221,6 +226,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = {
		.gmem_size = SZ_1M,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		.snapshot_size = SZ_1M,
		},
		.gpmu_tsens = 0x00060007,
		.max_power = 5448,
		@@ -233,6 +239,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = {
		.hwcg_count = ARRAY_SIZE(a530_hwcg_regs),
		.vbif = a530_vbif_regs,
		.vbif_count = ARRAY_SIZE(a530_vbif_regs),
		.highest_bank_bit = 15,
		};

		/* For a505, a506 and a508 */
		@@ -286,6 +293,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a505 = {
		.gmem_size = (SZ_128K + SZ_8K),
		.busy_mask = 0xfffffffe,
		.bus_width = 16,
		.snapshot_size = SZ_1M,
		},
		.pm4fw_name = "a530_pm4.fw",
		.pfpfw_name = "a530_pfp.fw",
		@@ -305,6 +313,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a506 = {
		.gmem_size = (SZ_128K + SZ_8K),
		.busy_mask = 0xfffffffe,
		.bus_width = 16,
		.snapshot_size = SZ_1M,
		},
		.pm4fw_name = "a530_pm4.fw",
		.pfpfw_name = "a530_pfp.fw",
		@@ -313,6 +322,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a506 = {
		.hwcg_count = ARRAY_SIZE(a50x_hwcg_regs),
		.vbif = a530_vbif_regs,
		.vbif_count = ARRAY_SIZE(a530_vbif_regs),
		.highest_bank_bit = 14,
		};

		static const struct adreno_reglist a510_hwcg_regs[] = {
		@@ -382,6 +392,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a510 = {
		.gmem_size = SZ_256K,
		.busy_mask = 0xfffffffe,
		.bus_width = 16,
		.snapshot_size = SZ_1M,
		},
		.pm4fw_name = "a530_pm4.fw",
		.pfpfw_name = "a530_pfp.fw",
		@@ -507,6 +518,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a540v2 = {
		.gmem_size = SZ_1M,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		.snapshot_size = SZ_1M,
		},
		.gpmu_tsens = 0x000c000d,
		.max_power = 5448,
		@@ -518,6 +530,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a540v2 = {
		.hwcg_count = ARRAY_SIZE(a540_hwcg_regs),
		.vbif = a540_vbif_regs,
		.vbif_count = ARRAY_SIZE(a540_vbif_regs),
		.highest_bank_bit = 15,
		};

		static const struct adreno_reglist a512_hwcg_regs[] = {
		@@ -589,12 +602,14 @@ static const struct adreno_a5xx_core adreno_gpu_core_a512 = {
		.gmem_size = (SZ_256K + SZ_16K),
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		.snapshot_size = SZ_1M,
		},
		.pm4fw_name = "a530_pm4.fw",
		.pfpfw_name = "a530_pfp.fw",
		.zap_name = "a512_zap",
		.hwcg = a512_hwcg_regs,
		.hwcg_count = ARRAY_SIZE(a512_hwcg_regs),
		.highest_bank_bit = 14,
		};

		static const struct adreno_a5xx_core adreno_gpu_core_a508 = {
		@@ -607,6 +622,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a508 = {
		.gmem_size = (SZ_128K + SZ_8K),
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		.snapshot_size = SZ_1M,
		},
		.pm4fw_name = "a530_pm4.fw",
		.pfpfw_name = "a530_pfp.fw",
		@@ -615,6 +631,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a508 = {
		.hwcg_count = ARRAY_SIZE(a50x_hwcg_regs),
		.vbif = a530_vbif_regs,
		.vbif_count = ARRAY_SIZE(a530_vbif_regs),
		.highest_bank_bit = 14,
		};

		DEFINE_DEPRECATED_CORE(a630v1, ADRENO_REV_A630, 6, 3, 0, 0);
		@@ -781,6 +798,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = {
		.gmem_size = SZ_1M,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		.snapshot_size = SZ_1M,
		},
		.prim_fifo_threshold = 0x0018000,
		.pdc_address_offset = 0x00030080,
		@@ -795,6 +813,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = {
		.vbif_count = ARRAY_SIZE(a630_vbif_regs),
		.hang_detect_cycles = 0xcfffff,
		.protected_regs = a630_protected_regs,
		.highest_bank_bit = 15,
		};

		/* For a615, a616 and a618 */
		@@ -880,6 +899,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = {
		.gmem_size = SZ_512K,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		.snapshot_size = 600 * SZ_1K,
		},
		.prim_fifo_threshold = 0x0018000,
		.pdc_address_offset = 0x00030080,
		@@ -894,6 +914,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = {
		.vbif_count = ARRAY_SIZE(a615_gbif_regs),
		.hang_detect_cycles = 0xcfffff,
		.protected_regs = a630_protected_regs,
		.highest_bank_bit = 14,
		};

		static const struct adreno_a6xx_core adreno_gpu_core_a618 = {
		@@ -907,6 +928,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = {
		.gmem_size = SZ_512K,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		.snapshot_size = SZ_1M,
		},
		.prim_fifo_threshold = 0x0018000,
		.pdc_address_offset = 0x00030090,
		@@ -921,6 +943,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = {
		.vbif_count = ARRAY_SIZE(a615_gbif_regs),
		.hang_detect_cycles = 0x3fffff,
		.protected_regs = a630_protected_regs,
		.highest_bank_bit = 14,
		};

		static const struct adreno_reglist a620_hwcg_regs[] = {
		@@ -1035,6 +1058,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = {
		.gmem_size = SZ_512K,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		.snapshot_size = 2 * SZ_1M,
		},
		.prim_fifo_threshold = 0x0010000,
		.pdc_address_offset = 0x000300a0,
		@@ -1051,6 +1075,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = {
		.hang_detect_cycles = 0x3ffff,
		.protected_regs = a620_protected_regs,
		.disable_tseskip = true,
		.highest_bank_bit = 14,
		};

		static const struct adreno_reglist a640_hwcg_regs[] = {
		@@ -1125,6 +1150,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = {
		.gmem_size = SZ_1M, //Verified 1MB
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		.snapshot_size = 2 * SZ_1M,
		},
		.prim_fifo_threshold = 0x00200000,
		.pdc_address_offset = 0x00030090,
		@@ -1140,6 +1166,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = {
		.hang_detect_cycles = 0xcfffff,
		.protected_regs = a630_protected_regs,
		.disable_tseskip = true,
		.highest_bank_bit = 15,
		};

		static const struct adreno_reglist a650_hwcg_regs[] = {
		@@ -1205,6 +1232,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = {
		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		.snapshot_size = 2 * SZ_1M,
		},
		.prim_fifo_threshold = 0x00300000,
		.pdc_address_offset = 0x000300A0,
		@@ -1220,6 +1248,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = {
		.hang_detect_cycles = 0xcfffff,
		.protected_regs = a620_protected_regs,
		.disable_tseskip = true,
		.highest_bank_bit = 16,
		};

		static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = {
		@@ -1234,6 +1263,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = {
		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		.snapshot_size = 2 * SZ_1M,
		},
		.prim_fifo_threshold = 0x00300000,
		.pdc_address_offset = 0x000300A0,
		@@ -1249,6 +1279,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = {
		.hang_detect_cycles = 0x3ffff,
		.protected_regs = a620_protected_regs,
		.disable_tseskip = true,
		.highest_bank_bit = 16,
		};

		static const struct adreno_a6xx_core adreno_gpu_core_a680 = {
		@@ -1260,6 +1291,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = {
		.gmem_size = SZ_2M,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		.snapshot_size = SZ_1M,
		},
		.prim_fifo_threshold = 0x00400000,
		.pdc_address_offset = 0x00030090,
		@@ -1275,6 +1307,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = {
		.hang_detect_cycles = 0xcfffff,
		.protected_regs = a630_protected_regs,
		.disable_tseskip = true,
		.highest_bank_bit = 16,
		};

		static const struct adreno_reglist a612_hwcg_regs[] = {
		@@ -1337,6 +1370,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = {
		.gmem_size = (SZ_128K + SZ_4K),
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		.snapshot_size = SZ_1M,
		},
		.prim_fifo_threshold = 0x00080000,
		.pdc_address_offset = 0x00030080,
		@@ -1349,6 +1383,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = {
		.vbif_count = ARRAY_SIZE(a640_vbif_regs),
		.hang_detect_cycles = 0x3fffff,
		.protected_regs = a630_protected_regs,
		.highest_bank_bit = 14,
		};

		static const struct adreno_a6xx_core adreno_gpu_core_a616 = {
		@@ -1362,6 +1397,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = {
		.gmem_size = SZ_512K,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		.snapshot_size = SZ_1M,
		},
		.prim_fifo_threshold = 0x0018000,
		.pdc_address_offset = 0x00030080,
		@@ -1376,6 +1412,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = {
		.vbif_count = ARRAY_SIZE(a615_gbif_regs),
		.hang_detect_cycles = 0xcfffff,
		.protected_regs = a630_protected_regs,
		.highest_bank_bit = 14,
		};

		static const struct adreno_a6xx_core adreno_gpu_core_a610 = {
		@@ -1398,6 +1435,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a610 = {
		.vbif_count = ARRAY_SIZE(a640_vbif_regs),
		.hang_detect_cycles = 0x3ffff,
		.protected_regs = a630_protected_regs,
		.highest_bank_bit = 14,
		};

		static const struct adreno_gpu_core *adreno_gpulist[] = {

drivers/gpu/msm/adreno.c

+101 −130

Original line number	Diff line number	Diff line
		@@ -3,6 +3,7 @@
		* Copyright (c) 2002,2007-2019, The Linux Foundation. All rights reserved.
		*/
		#include <linux/delay.h>
		#include <linux/firmware.h>
		#include <linux/input.h>
		#include <linux/io.h>
		#include <linux/of.h>
		@@ -46,9 +47,6 @@ static struct adreno_device device_3d0 = {
		.pwrscale = KGSL_PWRSCALE_INIT(&adreno_tz_data),
		.name = DEVICE_3D0_NAME,
		.id = 0,
		.pwrctrl = {
		.irq_name = "kgsl_3d0_irq",
		},
		.iomemname = "kgsl_3d0_reg_memory",
		.ftbl = &adreno_functable,
		},
		@@ -93,6 +91,39 @@ int adreno_wake_nice = -7;
		/* Number of milliseconds to stay active active after a wake on touch */
		unsigned int adreno_wake_timeout = 100;

		int adreno_get_firmware(struct adreno_device *adreno_dev,
		const char fwfile, struct adreno_firmware firmware)
		{
		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
		const struct firmware *fw = NULL;
		int ret;

		if (!IS_ERR_OR_NULL(firmware->memdesc))
		return 0;

		ret = request_firmware(&fw, fwfile, &device->pdev->dev);

		if (ret) {
		dev_err(device->dev, "request_firmware(%s) failed: %d\n",
		fwfile, ret);
		return ret;
		}

		firmware->memdesc = kgsl_allocate_global(device, fw->size - 4,
		KGSL_MEMFLAGS_GPUREADONLY, KGSL_MEMDESC_UCODE,
		"ucode");

		ret = PTR_ERR_OR_ZERO(firmware->memdesc);
		if (!ret) {
		memcpy(firmware->memdesc->hostptr, &fw->data[4], fw->size - 4);
		firmware->size = (fw->size - 4) / sizeof(u32);
		firmware->version = ((u32 )&fw->data[4]);
		}

		release_firmware(fw);
		return ret;
		}

		void adreno_reglist_write(struct adreno_device *adreno_dev,
		const struct adreno_reglist *list, u32 count)
		{
		@@ -164,29 +195,13 @@ unsigned int adreno_get_rptr(struct adreno_ringbuffer *rb)
		else {
		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

		kgsl_sharedmem_readl(&device->scratch, &rptr,
		kgsl_sharedmem_readl(device->scratch, &rptr,
		SCRATCH_RPTR_OFFSET(rb->id));
		}

		return rptr;
		}

		/**
		* adreno_of_read_property() - Adreno read property
		* @node: Device node
		*
		* Read a u32 property.
		*/
		static inline int adreno_of_read_property(struct device *dev,
		struct device_node node, const char prop, unsigned int *ptr)
		{
		int ret = of_property_read_u32(node, prop, ptr);

		if (ret)
		dev_err(dev, "%pOF: Unable to read '%s'\n", node, prop);
		return ret;
		}

		static void __iomem *efuse_base;
		static size_t efuse_len;

		@@ -262,18 +277,6 @@ static int _get_counter(struct adreno_device *adreno_dev,
		return ret;
		}

		static inline void _put_counter(struct adreno_device *adreno_dev,
		int group, int countable, unsigned int *lo,
		unsigned int *hi)
		{
		if (*lo != 0)
		adreno_perfcounter_put(adreno_dev, group, countable,
		PERFCOUNTER_FLAG_KERNEL);

		*lo = 0;
		*hi = 0;
		}

		/**
		* adreno_fault_detect_start() - Allocate performance counters
		* used for fast fault detection
		@@ -322,11 +325,16 @@ void adreno_fault_detect_stop(struct adreno_device *adreno_dev)
		return;

		for (i = 0; i < gpudev->ft_perf_counters_count; i++) {
		_put_counter(adreno_dev, gpudev->ft_perf_counters[i].counter,
		if (!adreno_ft_regs[j + (i * 2)])
		continue;

		adreno_perfcounter_put(adreno_dev,
		gpudev->ft_perf_counters[i].counter,
		gpudev->ft_perf_counters[i].countable,
		&adreno_ft_regs[j + (i * 2)],
		&adreno_ft_regs[j + ((i * 2) + 1)]);
		PERFCOUNTER_FLAG_KERNEL);

		adreno_ft_regs[j + (i * 2)] = 0;
		adreno_ft_regs[(j + (i * 2)) + 1] = 0;
		}

		adreno_dev->fast_hang_detect = 0;
		@@ -924,8 +932,11 @@ static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev,
		unsigned int index;
		struct kgsl_pwrlevel *level;

		if (adreno_of_read_property(device->dev, child, "reg", &index))
		if (of_property_read_u32(child, "reg", &index)) {
		dev_err(device->dev,
		"%pOF: powerlevel index not found\n", child);
		return -EINVAL;
		}

		if (index >= KGSL_MAX_PWRLEVELS) {
		dev_err(device->dev,
		@@ -939,9 +950,12 @@ static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev,

		level = &pwr->pwrlevels[index];

		if (adreno_of_read_property(device->dev, child, "qcom,gpu-freq",
		&level->gpu_freq))
		if (of_property_read_u32(child, "qcom,gpu-freq",
		&level->gpu_freq)) {
		dev_err(device->dev,
		"%pOF: Unable to read qcom,gpu-freq\n", child);
		return -EINVAL;
		}

		of_property_read_u32(child, "qcom,acd-level",
		&level->acd_level);
		@@ -1109,15 +1123,6 @@ static int adreno_of_get_power(struct adreno_device *adreno_dev,
		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
		struct device_node *node = pdev->dev.of_node;
		struct resource *res;
		unsigned int timeout;

		if (of_property_read_string(node, "label", &pdev->name)) {
		dev_err(device->dev, "Unable to read 'label'\n");
		return -EINVAL;
		}

		if (adreno_of_read_property(device->dev, node, "qcom,id", &pdev->id))
		return -EINVAL;

		/* Get starting physical address of device registers */
		res = platform_get_resource_byname(device->pdev, IORESOURCE_MEM,
		@@ -1144,10 +1149,8 @@ static int adreno_of_get_power(struct adreno_device *adreno_dev,

		l3_pwrlevel_probe(device, node);

		if (of_property_read_u32(node, "qcom,idle-timeout", &timeout))
		timeout = 80;

		device->pwrctrl.interval_timeout = msecs_to_jiffies(timeout);
		/* Default timeout is 80 ms across all targets */
		device->pwrctrl.interval_timeout = msecs_to_jiffies(80);

		device->pwrctrl.bus_control = of_property_read_bool(node,
		"qcom,bus-control");
		@@ -1344,7 +1347,8 @@ static int adreno_probe(struct platform_device *pdev)
		struct adreno_device *adreno_dev;
		struct kgsl_device *device;
		int status;
		unsigned int priv;
		unsigned int priv = 0;
		u32 size;

		of_id = of_match_device(adreno_match_table, &pdev->dev);
		if (!of_id)
		@@ -1430,17 +1434,30 @@ static int adreno_probe(struct platform_device *pdev)
		device->mmu.features \|= KGSL_MMU_IO_COHERENT;

		/* Allocate the memstore for storing timestamps and other useful info */
		priv = KGSL_MEMDESC_CONTIG;

		if (ADRENO_FEATURE(adreno_dev, ADRENO_APRIV))
		priv \|= KGSL_MEMDESC_PRIVILEGED;

		status = kgsl_allocate_global(device, &device->memstore,
		device->memstore = kgsl_allocate_global(device,
		KGSL_MEMSTORE_SIZE, 0, priv, "memstore");

		status = PTR_ERR_OR_ZERO(device->memstore);
		if (status)
		goto out;

		/* Initialize the snapshot engine */
		size = adreno_dev->gpucore->snapshot_size;

		/*
		* Use a default size if one wasn't specified, but print a warning so
		* the developer knows to fix it
		*/

		if (WARN(!size, "The snapshot size was not specified in the gpucore\n"))
		size = SZ_1M;

		kgsl_device_snapshot_probe(device, size);

		status = adreno_ringbuffer_probe(adreno_dev);
		if (status)
		goto out;
		@@ -1492,7 +1509,6 @@ static int adreno_probe(struct platform_device *pdev)
		out:
		if (status) {
		adreno_ringbuffer_close(adreno_dev);
		kgsl_free_global(device, &device->memstore);
		kgsl_device_platform_remove(device);
		device->pdev = NULL;
		}
		@@ -1502,13 +1518,9 @@ static int adreno_probe(struct platform_device *pdev)

		static void _adreno_free_memories(struct adreno_device *adreno_dev)
		{
		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
		struct adreno_firmware *pfp_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PFP);
		struct adreno_firmware *pm4_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PM4);

		if (test_bit(ADRENO_DEVICE_DRAWOBJ_PROFILE, &adreno_dev->priv))
		kgsl_free_global(device, &adreno_dev->profile_buffer);

		/* Free local copies of firmware and other command streams */
		kfree(pfp_fw->fwvirt);
		pfp_fw->fwvirt = NULL;
		@@ -1518,9 +1530,6 @@ static void _adreno_free_memories(struct adreno_device *adreno_dev)

		kfree(adreno_dev->gpmu_cmds);
		adreno_dev->gpmu_cmds = NULL;

		kgsl_free_global(device, &pfp_fw->memdesc);
		kgsl_free_global(device, &pm4_fw->memdesc);
		}

		static int adreno_remove(struct platform_device *pdev)
		@@ -1576,16 +1585,11 @@ static int adreno_remove(struct platform_device *pdev)
		if (efuse_base != NULL)
		iounmap(efuse_base);

		kgsl_free_global(device, &device->memstore);

		kgsl_device_platform_remove(device);

		gmu_core_remove(device);

		if (test_bit(ADRENO_DEVICE_PWRON_FIXUP, &adreno_dev->priv)) {
		kgsl_free_global(device, &adreno_dev->pwron_fixup);
		clear_bit(ADRENO_DEVICE_PWRON_FIXUP, &adreno_dev->priv);
		}
		clear_bit(ADRENO_DEVICE_INITIALIZED, &adreno_dev->priv);

		return 0;
		@@ -1694,10 +1698,6 @@ static int adreno_init(struct kgsl_device *device)
		struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
		int ret;

		if (!adreno_is_a3xx(adreno_dev))
		kgsl_sharedmem_set(device, &device->scratch, 0, 0,
		device->scratch.size);

		ret = kgsl_pwrctrl_change_state(device, KGSL_STATE_INIT);
		if (ret)
		return ret;
		@@ -1754,25 +1754,19 @@ static int adreno_init(struct kgsl_device *device)

		if (!adreno_is_a3xx(adreno_dev)) {
		unsigned int priv = 0;
		int r;

		if (ADRENO_FEATURE(adreno_dev, ADRENO_APRIV))
		priv \|= KGSL_MEMDESC_PRIVILEGED;

		r = kgsl_allocate_global(device,
		&adreno_dev->profile_buffer, PAGE_SIZE,
		0, priv, "alwayson");
		adreno_dev->profile_buffer =
		kgsl_allocate_global(device, PAGE_SIZE, 0, priv,
		"alwayson");

		adreno_dev->profile_index = 0;

		if (r == 0) {
		if (!IS_ERR(adreno_dev->profile_buffer))
		set_bit(ADRENO_DEVICE_DRAWOBJ_PROFILE,
		&adreno_dev->priv);
		kgsl_sharedmem_set(device,
		&adreno_dev->profile_buffer, 0, 0,
		PAGE_SIZE);
		}

		}

		return 0;
		@@ -1875,7 +1869,7 @@ static void adreno_set_active_ctxs_null(struct adreno_device *adreno_dev)
		rb->drawctxt_active = NULL;

		kgsl_sharedmem_writel(KGSL_DEVICE(adreno_dev),
		&rb->pagetable_desc, PT_INFO_OFFSET(current_rb_ptname),
		rb->pagetable_desc, PT_INFO_OFFSET(current_rb_ptname),
		0);
		}
		}
		@@ -2227,27 +2221,6 @@ static int adreno_stop(struct kgsl_device *device)
		return error;
		}

		static inline bool adreno_try_soft_reset(struct kgsl_device *device, int fault)
		{
		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

		/*
		* Do not do soft reset for a IOMMU fault (because the IOMMU hardware
		* needs a reset too) and also for below gpu
		* A304: It can't do SMMU programming of any kind after a soft reset
		* A612: IPC protocol between RGMU and CP will not restart after reset
		* A610: An across chip issue with reset line in all 11nm chips,
		* resulting in recommendation to not use soft reset
		*/

		if ((fault & ADRENO_IOMMU_PAGE_FAULT) \|\| adreno_is_a304(adreno_dev) \|\|
		adreno_is_a612(adreno_dev) \|\|
		adreno_is_a610(adreno_dev))
		return false;

		return true;
		}

		/**
		* adreno_reset() - Helper function to reset the GPU
		* @device: Pointer to the KGSL device structure for the GPU
		@@ -2263,8 +2236,14 @@ int adreno_reset(struct kgsl_device *device, int fault)
		int ret = -EINVAL;
		int i = 0;

		/* Try soft reset first */
		if (adreno_try_soft_reset(device, fault)) {
		/*
		* Try soft reset first Do not do soft reset for a IOMMU fault (because
		* the IOMMU hardware needs a reset too) or for the A304 because it
		* can't do SMMU programming of any kind after a soft reset
		*/

		if (!(fault & ADRENO_IOMMU_PAGE_FAULT) && !adreno_is_a304(adreno_dev)
		&& !adreno_is_a612(adreno_dev) && !adreno_is_a610(adreno_dev)) {
		/* Make sure VBIF is cleared before resetting */
		ret = adreno_clear_pending_transactions(device);

		@@ -2347,14 +2326,14 @@ static int adreno_prop_device_shadow(struct kgsl_device *device,
		{
		struct kgsl_shadowprop shadowprop = { 0 };

		if (device->memstore.hostptr) {
		if (device->memstore->hostptr) {
		/*
		* NOTE: with mmu enabled, gpuaddr doesn't mean
		* anything to mmap().
		*/

		shadowprop.gpuaddr = (unsigned long)device->memstore.gpuaddr;
		shadowprop.size = device->memstore.size;
		shadowprop.gpuaddr = (unsigned long)device->memstore->gpuaddr;
		shadowprop.size = device->memstore->size;

		shadowprop.flags = KGSL_FLAGS_INITIALIZED \|
		KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS;
		@@ -2367,11 +2346,10 @@ static int adreno_prop_device_qdss_stm(struct kgsl_device *device,
		struct kgsl_device_getproperty *param)
		{
		struct kgsl_qdss_stm_prop qdssprop = {0};
		struct kgsl_memdesc *qdss_desc = kgsl_mmu_get_qdss_global_entry(device);

		if (qdss_desc) {
		qdssprop.gpuaddr = qdss_desc->gpuaddr;
		qdssprop.size = qdss_desc->size;
		if (!IS_ERR_OR_NULL(device->qdss_desc)) {
		qdssprop.gpuaddr = device->qdss_desc->gpuaddr;
		qdssprop.size = device->qdss_desc->size;
		}

		return copy_prop(param, &qdssprop, sizeof(qdssprop));
		@@ -2381,12 +2359,10 @@ static int adreno_prop_device_qtimer(struct kgsl_device *device,
		struct kgsl_device_getproperty *param)
		{
		struct kgsl_qtimer_prop qtimerprop = {0};
		struct kgsl_memdesc *qtimer_desc =
		kgsl_mmu_get_qtimer_global_entry(device);

		if (qtimer_desc) {
		qtimerprop.gpuaddr = qtimer_desc->gpuaddr;
		qtimerprop.size = qtimer_desc->size;
		if (!IS_ERR_OR_NULL(device->qtimer_desc)) {
		qtimerprop.gpuaddr = device->qtimer_desc->gpuaddr;
		qtimerprop.size = device->qtimer_desc->size;
		}

		return copy_prop(param, &qtimerprop, sizeof(qtimerprop));
		@@ -3394,11 +3370,11 @@ static int __adreno_readtimestamp(struct adreno_device *adreno_dev, int index,

		switch (type) {
		case KGSL_TIMESTAMP_CONSUMED:
		kgsl_sharedmem_readl(&device->memstore, timestamp,
		kgsl_sharedmem_readl(device->memstore, timestamp,
		KGSL_MEMSTORE_OFFSET(index, soptimestamp));
		break;
		case KGSL_TIMESTAMP_RETIRED:
		kgsl_sharedmem_readl(&device->memstore, timestamp,
		kgsl_sharedmem_readl(device->memstore, timestamp,
		KGSL_MEMSTORE_OFFSET(index, eoptimestamp));
		break;
		default:
		@@ -3514,12 +3490,6 @@ static void adreno_device_private_destroy(struct kgsl_device_private *dev_priv)
		kfree(adreno_priv);
		}

		static inline s64 adreno_ticks_to_us(u32 ticks, u32 freq)
		{
		freq /= 1000000;
		return ticks / freq;
		}

		/**
		* adreno_power_stats() - Reads the counters needed for freq decisions
		* @device: Pointer to device whose counters are read
		@@ -3556,8 +3526,9 @@ static void adreno_power_stats(struct kgsl_device *device,
		do_div(stats->busy_time, 192);
		} else {
		/* clock sourced from GFX3D */
		stats->busy_time = adreno_ticks_to_us(gpu_busy,
		kgsl_pwrctrl_active_freq(pwr));
		s64 freq = kgsl_pwrctrl_active_freq(pwr) / 1000000;

		stats->busy_time = gpu_busy / freq;
		}

		if (device->pwrctrl.bus_control) {
		@@ -3790,7 +3761,7 @@ static struct platform_driver adreno_platform_driver = {
		.resume = kgsl_resume_driver,
		.id_table = adreno_id_table,
		.driver = {
		.name = DEVICE_3D_NAME,
		.name = "kgsl-3d",
		.pm = &kgsl_pm_ops,
		.of_match_table = adreno_match_table,
		}

drivers/gpu/msm/adreno.h

+30 −14

Original line number	Diff line number	Diff line
		@@ -13,7 +13,6 @@
		#include "adreno_ringbuffer.h"
		#include "kgsl_sharedmem.h"

		#define DEVICE_3D_NAME "kgsl-3d"
		#define DEVICE_3D0_NAME "kgsl-3d0"

		/* ADRENO_DEVICE - Given a kgsl_device return the adreno device struct */
		@@ -271,7 +270,7 @@ enum adreno_preempt_states {
		*/
		struct adreno_preemption {
		atomic_t state;
		struct kgsl_memdesc counters;
		struct kgsl_memdesc *counters;
		struct timer_list timer;
		struct work_struct work;
		unsigned int preempt_level;
		@@ -304,7 +303,7 @@ struct adreno_firmware {
		unsigned int *fwvirt;
		size_t size;
		unsigned int version;
		struct kgsl_memdesc memdesc;
		struct kgsl_memdesc *memdesc;
		};

		/**
		@@ -363,6 +362,8 @@ struct adreno_gpu_core {
		size_t gmem_size;
		unsigned int busy_mask;
		u32 bus_width;
		/** @snapshot_size: Size of the static snapshot region in bytes */
		u32 snapshot_size;
		};

		/**
		@@ -480,7 +481,7 @@ struct adreno_device {
		bool cooperative_reset;
		struct adreno_profile profile;
		struct adreno_dispatcher dispatcher;
		struct kgsl_memdesc pwron_fixup;
		struct kgsl_memdesc *pwron_fixup;
		unsigned int pwron_fixup_dwords;
		struct work_struct input_work;
		struct adreno_busy_data busy_data;
		@@ -497,9 +498,9 @@ struct adreno_device {
		struct dentry *ctx_d_debugfs;
		unsigned long pwrctrl_flag;

		struct kgsl_memdesc profile_buffer;
		struct kgsl_memdesc *profile_buffer;
		unsigned int profile_index;
		struct kgsl_memdesc pwrup_reglist;
		struct kgsl_memdesc *pwrup_reglist;
		uint32_t *lm_sequence;
		uint32_t lm_size;
		struct adreno_preemption preempt;
		@@ -528,6 +529,10 @@ struct adreno_device {
		bool gpuhtw_llc_slice_enable;
		unsigned int zap_loaded;
		unsigned int soc_hw_rev;
		/**
		* @critpkts: Memory descriptor for 5xx critical packets if applicable
		*/
		struct kgsl_memdesc *critpkts;
		};

		/**
		@@ -593,10 +598,7 @@ struct adreno_drawobj_profile_entry {
		* and are indexed by the enumeration values defined in this enum
		*/
		enum adreno_regs {
		ADRENO_REG_CP_ME_RAM_WADDR,
		ADRENO_REG_CP_ME_RAM_DATA,
		ADRENO_REG_CP_PFP_UCODE_DATA,
		ADRENO_REG_CP_PFP_UCODE_ADDR,
		ADRENO_REG_CP_RB_BASE,
		ADRENO_REG_CP_RB_BASE_HI,
		ADRENO_REG_CP_RB_RPTR_ADDR_LO,
		@@ -615,7 +617,6 @@ enum adreno_regs {
		ADRENO_REG_CP_TIMESTAMP,
		ADRENO_REG_CP_SCRATCH_REG6,
		ADRENO_REG_CP_SCRATCH_REG7,
		ADRENO_REG_CP_ME_RAM_RADDR,
		ADRENO_REG_CP_ROQ_ADDR,
		ADRENO_REG_CP_ROQ_DATA,
		ADRENO_REG_CP_MEQ_ADDR,
		@@ -1509,7 +1510,7 @@ static inline void adreno_ringbuffer_set_global(
		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

		kgsl_sharedmem_writel(device,
		&adreno_dev->ringbuffers[0].pagetable_desc,
		adreno_dev->ringbuffers[0].pagetable_desc,
		PT_INFO_OFFSET(current_global_ptname), name);
		}

		@@ -1522,13 +1523,13 @@ static inline void adreno_ringbuffer_set_pagetable(struct adreno_ringbuffer *rb,

		spin_lock_irqsave(&rb->preempt_lock, flags);

		kgsl_sharedmem_writel(device, &rb->pagetable_desc,
		kgsl_sharedmem_writel(device, rb->pagetable_desc,
		PT_INFO_OFFSET(current_rb_ptname), pt->name);

		kgsl_sharedmem_writeq(device, &rb->pagetable_desc,
		kgsl_sharedmem_writeq(device, rb->pagetable_desc,
		PT_INFO_OFFSET(ttbr0), kgsl_mmu_pagetable_get_ttbr0(pt));

		kgsl_sharedmem_writel(device, &rb->pagetable_desc,
		kgsl_sharedmem_writel(device, rb->pagetable_desc,
		PT_INFO_OFFSET(contextidr),
		kgsl_mmu_pagetable_get_contextidr(pt));

		@@ -1689,4 +1690,19 @@ int adreno_gmu_fenced_write(struct adreno_device *adreno_dev,
		unsigned int fence_mask);
		int adreno_clear_pending_transactions(struct kgsl_device *device);
		void adreno_gmu_send_nmi(struct adreno_device *adreno_dev);


		/**
		* adreno_get_firwmare - Load firmware into a adreno_firmware struct
		* @adreno_dev: An Adreno GPU device handle
		* @fwfile: Firmware file to load
		* @firmware: A &struct adreno_firmware container for the firmware.
		*
		* Load the specified firmware file into the memdesc in &struct adreno_firmware
		* and get the size and version from the data.
		*
		* Return: 0 on success or negative on failure
		*/
		int adreno_get_firmware(struct adreno_device *adreno_dev,
		const char fwfile, struct adreno_firmware firmware);
		#endif /__ADRENO_H /

drivers/gpu/msm/adreno_a3xx.c

+23 −66

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/msm/adreno_a5xx.c

+27 −76

File changed.

Preview size limit exceeded, changes collapsed.