Loading dsp/q6afe.c +1 −1 Original line number Diff line number Diff line Loading @@ -276,7 +276,7 @@ static struct afe_clkinfo_per_port clkinfo_per_port[] = { MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, { AFE_PORT_ID_QUINARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT, MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, { AFE_PORT_ID_SENARY_MI2S_TX, Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT, { AFE_PORT_ID_SENARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT, MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, { AFE_PORT_ID_PRIMARY_PCM_RX, Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT, MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, Loading Loading
dsp/q6afe.c +1 −1 Original line number Diff line number Diff line Loading @@ -276,7 +276,7 @@ static struct afe_clkinfo_per_port clkinfo_per_port[] = { MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, { AFE_PORT_ID_QUINARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT, MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, { AFE_PORT_ID_SENARY_MI2S_TX, Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT, { AFE_PORT_ID_SENARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT, MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, { AFE_PORT_ID_PRIMARY_PCM_RX, Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT, MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, Loading