disp: pll: update SSC offset value



This change updates SSC offset value according to recent
hardware recommendation.

Change-Id: Ie822ed6ae8e383f93ca91615617dad4b4324b8a0
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>

parent 4be499df

pll/dsi_pll_7nm.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -483,7 +483,7 @@ static void dsi_pll_setup_config(struct dsi_pll_7nm *pll,
		config->frac_bits = 18;
		config->lock_timer = 64;
		config->ssc_freq = 31500;
		config->ssc_offset = 5000;
		config->ssc_offset = 4800;
		config->ssc_adj_per = 2;
		config->thresh_cycles = 32;
		config->refclk_cycles = 256;