msm: kgsl: Move globals to the KGSL device handle (2f23b00d) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/gpu/msm/adreno.c

+54 −45

Original line number	Original line	Diff line number	Diff line
	@@ -3,6 +3,7 @@
	* Copyright (c) 2002,2007-2019, The Linux Foundation. All rights reserved.		* Copyright (c) 2002,2007-2019, The Linux Foundation. All rights reserved.
	*/		*/
	#include <linux/delay.h>		#include <linux/delay.h>
			#include <linux/firmware.h>
	#include <linux/input.h>		#include <linux/input.h>
	#include <linux/io.h>		#include <linux/io.h>
	#include <linux/of.h>		#include <linux/of.h>
	@@ -90,6 +91,39 @@ int adreno_wake_nice = -7;
	/* Number of milliseconds to stay active active after a wake on touch */		/* Number of milliseconds to stay active active after a wake on touch */
	unsigned int adreno_wake_timeout = 100;		unsigned int adreno_wake_timeout = 100;

			int adreno_get_firmware(struct adreno_device *adreno_dev,
			const char fwfile, struct adreno_firmware firmware)
			{
			struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
			const struct firmware *fw = NULL;
			int ret;

			if (!IS_ERR_OR_NULL(firmware->memdesc))
			return 0;

			ret = request_firmware(&fw, fwfile, &device->pdev->dev);

			if (ret) {
			dev_err(device->dev, "request_firmware(%s) failed: %d\n",
			fwfile, ret);
			return ret;
			}

			firmware->memdesc = kgsl_allocate_global(device, fw->size - 4,
			KGSL_MEMFLAGS_GPUREADONLY, KGSL_MEMDESC_UCODE,
			"ucode");

			ret = PTR_ERR_OR_ZERO(firmware->memdesc);
			if (!ret) {
			memcpy(firmware->memdesc->hostptr, &fw->data[4], fw->size - 4);
			firmware->size = (fw->size - 4) / sizeof(u32);
			firmware->version = ((u32 )&fw->data[4]);
			}

			release_firmware(fw);
			return ret;
			}

	void adreno_reglist_write(struct adreno_device *adreno_dev,		void adreno_reglist_write(struct adreno_device *adreno_dev,
	const struct adreno_reglist *list, u32 count)		const struct adreno_reglist *list, u32 count)
	{		{
	@@ -161,7 +195,7 @@ unsigned int adreno_get_rptr(struct adreno_ringbuffer *rb)
	else {		else {
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	kgsl_sharedmem_readl(&device->scratch, &rptr,		kgsl_sharedmem_readl(device->scratch, &rptr,
	SCRATCH_RPTR_OFFSET(rb->id));		SCRATCH_RPTR_OFFSET(rb->id));
	}		}

	@@ -1404,9 +1438,10 @@ static int adreno_probe(struct platform_device *pdev)
	if (ADRENO_FEATURE(adreno_dev, ADRENO_APRIV))		if (ADRENO_FEATURE(adreno_dev, ADRENO_APRIV))
	priv \|= KGSL_MEMDESC_PRIVILEGED;		priv \|= KGSL_MEMDESC_PRIVILEGED;

	status = kgsl_allocate_global(device, &device->memstore,		device->memstore = kgsl_allocate_global(device,
	KGSL_MEMSTORE_SIZE, 0, priv, "memstore");		KGSL_MEMSTORE_SIZE, 0, priv, "memstore");

			status = PTR_ERR_OR_ZERO(device->memstore);
	if (status)		if (status)
	goto out;		goto out;

	@@ -1474,7 +1509,6 @@ static int adreno_probe(struct platform_device *pdev)
	out:		out:
	if (status) {		if (status) {
	adreno_ringbuffer_close(adreno_dev);		adreno_ringbuffer_close(adreno_dev);
	kgsl_free_global(device, &device->memstore);
	kgsl_device_platform_remove(device);		kgsl_device_platform_remove(device);
	device->pdev = NULL;		device->pdev = NULL;
	}		}
	@@ -1484,13 +1518,9 @@ static int adreno_probe(struct platform_device *pdev)

	static void _adreno_free_memories(struct adreno_device *adreno_dev)		static void _adreno_free_memories(struct adreno_device *adreno_dev)
	{		{
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
	struct adreno_firmware *pfp_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PFP);		struct adreno_firmware *pfp_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PFP);
	struct adreno_firmware *pm4_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PM4);		struct adreno_firmware *pm4_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PM4);

	if (test_bit(ADRENO_DEVICE_DRAWOBJ_PROFILE, &adreno_dev->priv))
	kgsl_free_global(device, &adreno_dev->profile_buffer);

	/* Free local copies of firmware and other command streams */		/* Free local copies of firmware and other command streams */
	kfree(pfp_fw->fwvirt);		kfree(pfp_fw->fwvirt);
	pfp_fw->fwvirt = NULL;		pfp_fw->fwvirt = NULL;
	@@ -1500,9 +1530,6 @@ static void _adreno_free_memories(struct adreno_device *adreno_dev)

	kfree(adreno_dev->gpmu_cmds);		kfree(adreno_dev->gpmu_cmds);
	adreno_dev->gpmu_cmds = NULL;		adreno_dev->gpmu_cmds = NULL;

	kgsl_free_global(device, &pfp_fw->memdesc);
	kgsl_free_global(device, &pm4_fw->memdesc);
	}		}

	static int adreno_remove(struct platform_device *pdev)		static int adreno_remove(struct platform_device *pdev)
	@@ -1558,16 +1585,11 @@ static int adreno_remove(struct platform_device *pdev)
	if (efuse_base != NULL)		if (efuse_base != NULL)
	iounmap(efuse_base);		iounmap(efuse_base);

	kgsl_free_global(device, &device->memstore);

	kgsl_device_platform_remove(device);		kgsl_device_platform_remove(device);

	gmu_core_remove(device);		gmu_core_remove(device);

	if (test_bit(ADRENO_DEVICE_PWRON_FIXUP, &adreno_dev->priv)) {
	kgsl_free_global(device, &adreno_dev->pwron_fixup);
	clear_bit(ADRENO_DEVICE_PWRON_FIXUP, &adreno_dev->priv);		clear_bit(ADRENO_DEVICE_PWRON_FIXUP, &adreno_dev->priv);
	}
	clear_bit(ADRENO_DEVICE_INITIALIZED, &adreno_dev->priv);		clear_bit(ADRENO_DEVICE_INITIALIZED, &adreno_dev->priv);

	return 0;		return 0;
	@@ -1676,10 +1698,6 @@ static int adreno_init(struct kgsl_device *device)
	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);		struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
	int ret;		int ret;

	if (!adreno_is_a3xx(adreno_dev))
	kgsl_sharedmem_set(device, &device->scratch, 0, 0,
	device->scratch.size);

	ret = kgsl_pwrctrl_change_state(device, KGSL_STATE_INIT);		ret = kgsl_pwrctrl_change_state(device, KGSL_STATE_INIT);
	if (ret)		if (ret)
	return ret;		return ret;
	@@ -1736,25 +1754,19 @@ static int adreno_init(struct kgsl_device *device)

	if (!adreno_is_a3xx(adreno_dev)) {		if (!adreno_is_a3xx(adreno_dev)) {
	unsigned int priv = 0;		unsigned int priv = 0;
	int r;

	if (ADRENO_FEATURE(adreno_dev, ADRENO_APRIV))		if (ADRENO_FEATURE(adreno_dev, ADRENO_APRIV))
	priv \|= KGSL_MEMDESC_PRIVILEGED;		priv \|= KGSL_MEMDESC_PRIVILEGED;

	r = kgsl_allocate_global(device,		adreno_dev->profile_buffer =
	&adreno_dev->profile_buffer, PAGE_SIZE,		kgsl_allocate_global(device, PAGE_SIZE, 0, priv,
	0, priv, "alwayson");		"alwayson");

	adreno_dev->profile_index = 0;		adreno_dev->profile_index = 0;

	if (r == 0) {		if (!IS_ERR(adreno_dev->profile_buffer))
	set_bit(ADRENO_DEVICE_DRAWOBJ_PROFILE,		set_bit(ADRENO_DEVICE_DRAWOBJ_PROFILE,
	&adreno_dev->priv);		&adreno_dev->priv);
	kgsl_sharedmem_set(device,
	&adreno_dev->profile_buffer, 0, 0,
	PAGE_SIZE);
	}

	}		}

	return 0;		return 0;
	@@ -1857,7 +1869,7 @@ static void adreno_set_active_ctxs_null(struct adreno_device *adreno_dev)
	rb->drawctxt_active = NULL;		rb->drawctxt_active = NULL;

	kgsl_sharedmem_writel(KGSL_DEVICE(adreno_dev),		kgsl_sharedmem_writel(KGSL_DEVICE(adreno_dev),
	&rb->pagetable_desc, PT_INFO_OFFSET(current_rb_ptname),		rb->pagetable_desc, PT_INFO_OFFSET(current_rb_ptname),
	0);		0);
	}		}
	}		}
	@@ -2314,14 +2326,14 @@ static int adreno_prop_device_shadow(struct kgsl_device *device,
	{		{
	struct kgsl_shadowprop shadowprop = { 0 };		struct kgsl_shadowprop shadowprop = { 0 };

	if (device->memstore.hostptr) {		if (device->memstore->hostptr) {
	/*		/*
	* NOTE: with mmu enabled, gpuaddr doesn't mean		* NOTE: with mmu enabled, gpuaddr doesn't mean
	* anything to mmap().		* anything to mmap().
	*/		*/

	shadowprop.gpuaddr = (unsigned long)device->memstore.gpuaddr;		shadowprop.gpuaddr = (unsigned long)device->memstore->gpuaddr;
	shadowprop.size = device->memstore.size;		shadowprop.size = device->memstore->size;

	shadowprop.flags = KGSL_FLAGS_INITIALIZED \|		shadowprop.flags = KGSL_FLAGS_INITIALIZED \|
	KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS;		KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS;
	@@ -2334,11 +2346,10 @@ static int adreno_prop_device_qdss_stm(struct kgsl_device *device,
	struct kgsl_device_getproperty *param)		struct kgsl_device_getproperty *param)
	{		{
	struct kgsl_qdss_stm_prop qdssprop = {0};		struct kgsl_qdss_stm_prop qdssprop = {0};
	struct kgsl_memdesc *qdss_desc = kgsl_mmu_get_qdss_global_entry(device);

	if (qdss_desc) {		if (!IS_ERR_OR_NULL(device->qdss_desc)) {
	qdssprop.gpuaddr = qdss_desc->gpuaddr;		qdssprop.gpuaddr = device->qdss_desc->gpuaddr;
	qdssprop.size = qdss_desc->size;		qdssprop.size = device->qdss_desc->size;
	}		}

	return copy_prop(param, &qdssprop, sizeof(qdssprop));		return copy_prop(param, &qdssprop, sizeof(qdssprop));
	@@ -2348,12 +2359,10 @@ static int adreno_prop_device_qtimer(struct kgsl_device *device,
	struct kgsl_device_getproperty *param)		struct kgsl_device_getproperty *param)
	{		{
	struct kgsl_qtimer_prop qtimerprop = {0};		struct kgsl_qtimer_prop qtimerprop = {0};
	struct kgsl_memdesc *qtimer_desc =
	kgsl_mmu_get_qtimer_global_entry(device);

	if (qtimer_desc) {		if (!IS_ERR_OR_NULL(device->qtimer_desc)) {
	qtimerprop.gpuaddr = qtimer_desc->gpuaddr;		qtimerprop.gpuaddr = device->qtimer_desc->gpuaddr;
	qtimerprop.size = qtimer_desc->size;		qtimerprop.size = device->qtimer_desc->size;
	}		}

	return copy_prop(param, &qtimerprop, sizeof(qtimerprop));		return copy_prop(param, &qtimerprop, sizeof(qtimerprop));
	@@ -3361,11 +3370,11 @@ static int __adreno_readtimestamp(struct adreno_device *adreno_dev, int index,

	switch (type) {		switch (type) {
	case KGSL_TIMESTAMP_CONSUMED:		case KGSL_TIMESTAMP_CONSUMED:
	kgsl_sharedmem_readl(&device->memstore, timestamp,		kgsl_sharedmem_readl(device->memstore, timestamp,
	KGSL_MEMSTORE_OFFSET(index, soptimestamp));		KGSL_MEMSTORE_OFFSET(index, soptimestamp));
	break;		break;
	case KGSL_TIMESTAMP_RETIRED:		case KGSL_TIMESTAMP_RETIRED:
	kgsl_sharedmem_readl(&device->memstore, timestamp,		kgsl_sharedmem_readl(device->memstore, timestamp,
	KGSL_MEMSTORE_OFFSET(index, eoptimestamp));		KGSL_MEMSTORE_OFFSET(index, eoptimestamp));
	break;		break;
	default:		default:

drivers/gpu/msm/adreno.h

+28 −9

Original line number	Original line	Diff line number	Diff line
	@@ -270,7 +270,7 @@ enum adreno_preempt_states {
	*/		*/
	struct adreno_preemption {		struct adreno_preemption {
	atomic_t state;		atomic_t state;
	struct kgsl_memdesc counters;		struct kgsl_memdesc *counters;
	struct timer_list timer;		struct timer_list timer;
	struct work_struct work;		struct work_struct work;
	unsigned int preempt_level;		unsigned int preempt_level;
	@@ -303,7 +303,7 @@ struct adreno_firmware {
	unsigned int *fwvirt;		unsigned int *fwvirt;
	size_t size;		size_t size;
	unsigned int version;		unsigned int version;
	struct kgsl_memdesc memdesc;		struct kgsl_memdesc *memdesc;
	};		};

	/**		/**
	@@ -481,7 +481,7 @@ struct adreno_device {
	bool cooperative_reset;		bool cooperative_reset;
	struct adreno_profile profile;		struct adreno_profile profile;
	struct adreno_dispatcher dispatcher;		struct adreno_dispatcher dispatcher;
	struct kgsl_memdesc pwron_fixup;		struct kgsl_memdesc *pwron_fixup;
	unsigned int pwron_fixup_dwords;		unsigned int pwron_fixup_dwords;
	struct work_struct input_work;		struct work_struct input_work;
	struct adreno_busy_data busy_data;		struct adreno_busy_data busy_data;
	@@ -498,9 +498,9 @@ struct adreno_device {
	struct dentry *ctx_d_debugfs;		struct dentry *ctx_d_debugfs;
	unsigned long pwrctrl_flag;		unsigned long pwrctrl_flag;

	struct kgsl_memdesc profile_buffer;		struct kgsl_memdesc *profile_buffer;
	unsigned int profile_index;		unsigned int profile_index;
	struct kgsl_memdesc pwrup_reglist;		struct kgsl_memdesc *pwrup_reglist;
	uint32_t *lm_sequence;		uint32_t *lm_sequence;
	uint32_t lm_size;		uint32_t lm_size;
	struct adreno_preemption preempt;		struct adreno_preemption preempt;
	@@ -529,6 +529,10 @@ struct adreno_device {
	bool gpuhtw_llc_slice_enable;		bool gpuhtw_llc_slice_enable;
	unsigned int zap_loaded;		unsigned int zap_loaded;
	unsigned int soc_hw_rev;		unsigned int soc_hw_rev;
			/**
			* @critpkts: Memory descriptor for 5xx critical packets if applicable
			*/
			struct kgsl_memdesc *critpkts;
	};		};

	/**		/**
	@@ -1506,7 +1510,7 @@ static inline void adreno_ringbuffer_set_global(
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	kgsl_sharedmem_writel(device,		kgsl_sharedmem_writel(device,
	&adreno_dev->ringbuffers[0].pagetable_desc,		adreno_dev->ringbuffers[0].pagetable_desc,
	PT_INFO_OFFSET(current_global_ptname), name);		PT_INFO_OFFSET(current_global_ptname), name);
	}		}

	@@ -1519,13 +1523,13 @@ static inline void adreno_ringbuffer_set_pagetable(struct adreno_ringbuffer *rb,

	spin_lock_irqsave(&rb->preempt_lock, flags);		spin_lock_irqsave(&rb->preempt_lock, flags);

	kgsl_sharedmem_writel(device, &rb->pagetable_desc,		kgsl_sharedmem_writel(device, rb->pagetable_desc,
	PT_INFO_OFFSET(current_rb_ptname), pt->name);		PT_INFO_OFFSET(current_rb_ptname), pt->name);

	kgsl_sharedmem_writeq(device, &rb->pagetable_desc,		kgsl_sharedmem_writeq(device, rb->pagetable_desc,
	PT_INFO_OFFSET(ttbr0), kgsl_mmu_pagetable_get_ttbr0(pt));		PT_INFO_OFFSET(ttbr0), kgsl_mmu_pagetable_get_ttbr0(pt));

	kgsl_sharedmem_writel(device, &rb->pagetable_desc,		kgsl_sharedmem_writel(device, rb->pagetable_desc,
	PT_INFO_OFFSET(contextidr),		PT_INFO_OFFSET(contextidr),
	kgsl_mmu_pagetable_get_contextidr(pt));		kgsl_mmu_pagetable_get_contextidr(pt));

	@@ -1686,4 +1690,19 @@ int adreno_gmu_fenced_write(struct adreno_device *adreno_dev,
	unsigned int fence_mask);		unsigned int fence_mask);
	int adreno_clear_pending_transactions(struct kgsl_device *device);		int adreno_clear_pending_transactions(struct kgsl_device *device);
	void adreno_gmu_send_nmi(struct adreno_device *adreno_dev);		void adreno_gmu_send_nmi(struct adreno_device *adreno_dev);


			/**
			* adreno_get_firwmare - Load firmware into a adreno_firmware struct
			* @adreno_dev: An Adreno GPU device handle
			* @fwfile: Firmware file to load
			* @firmware: A &struct adreno_firmware container for the firmware.
			*
			* Load the specified firmware file into the memdesc in &struct adreno_firmware
			* and get the size and version from the data.
			*
			* Return: 0 on success or negative on failure
			*/
			int adreno_get_firmware(struct adreno_device *adreno_dev,
			const char fwfile, struct adreno_firmware firmware);
	#endif /__ADRENO_H /		#endif /__ADRENO_H /

drivers/gpu/msm/adreno_a3xx.c

+7 −9

Original line number	Original line	Diff line number	Diff line
	@@ -177,20 +177,18 @@ static int _a3xx_pwron_fixup(struct adreno_device *adreno_dev)
	{		{
	unsigned int *cmds;		unsigned int *cmds;
	int count = ARRAY_SIZE(_a3xx_pwron_fixup_fs_instructions);		int count = ARRAY_SIZE(_a3xx_pwron_fixup_fs_instructions);
	int ret;

	/* Return if the fixup is already in place */		/* Return if the fixup is already in place */
	if (test_bit(ADRENO_DEVICE_PWRON_FIXUP, &adreno_dev->priv))		if (test_bit(ADRENO_DEVICE_PWRON_FIXUP, &adreno_dev->priv))
	return 0;		return 0;

	ret = kgsl_allocate_global(KGSL_DEVICE(adreno_dev),		adreno_dev->pwron_fixup = kgsl_allocate_global(KGSL_DEVICE(adreno_dev),
	&adreno_dev->pwron_fixup, PAGE_SIZE,		PAGE_SIZE, KGSL_MEMFLAGS_GPUREADONLY, 0, "pwron_fixup");
	KGSL_MEMFLAGS_GPUREADONLY, 0, "pwron_fixup");

	if (ret)		if (IS_ERR(adreno_dev->pwron_fixup))
	return ret;		return PTR_ERR(adreno_dev->pwron_fixup);

	cmds = adreno_dev->pwron_fixup.hostptr;		cmds = adreno_dev->pwron_fixup->hostptr;

	*cmds++ = cp_type0_packet(A3XX_UCHE_CACHE_INVALIDATE0_REG, 2);		*cmds++ = cp_type0_packet(A3XX_UCHE_CACHE_INVALIDATE0_REG, 2);
	*cmds++ = 0x00000000;		*cmds++ = 0x00000000;
	@@ -598,7 +596,7 @@ static int _a3xx_pwron_fixup(struct adreno_device *adreno_dev)
	* program the indirect buffer call in the ringbuffer		* program the indirect buffer call in the ringbuffer
	*/		*/
	adreno_dev->pwron_fixup_dwords =		adreno_dev->pwron_fixup_dwords =
	(cmds - (unsigned int *) adreno_dev->pwron_fixup.hostptr);		(cmds - (unsigned int *) adreno_dev->pwron_fixup->hostptr);

	/* Mark the flag in ->priv to show that we have the fix */		/* Mark the flag in ->priv to show that we have the fix */
	set_bit(ADRENO_DEVICE_PWRON_FIXUP, &adreno_dev->priv);		set_bit(ADRENO_DEVICE_PWRON_FIXUP, &adreno_dev->priv);
	@@ -678,7 +676,7 @@ static int a3xx_rb_start(struct adreno_device *adreno_dev)
	(1 << 27));		(1 << 27));

	adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_BASE,		adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_BASE,
	rb->buffer_desc.gpuaddr);		rb->buffer_desc->gpuaddr);

	a3xx_microcode_load(adreno_dev);		a3xx_microcode_load(adreno_dev);

drivers/gpu/msm/adreno_a5xx.c

+23 −63

Original line number	Original line	Diff line number	Diff line
	@@ -19,8 +19,6 @@
	#include "kgsl_trace.h"		#include "kgsl_trace.h"

	static int critical_packet_constructed;		static int critical_packet_constructed;

	static struct kgsl_memdesc crit_pkts;
	static unsigned int crit_pkts_dwords;		static unsigned int crit_pkts_dwords;
	static struct kgsl_memdesc crit_pkts_refbuf0;		static struct kgsl_memdesc crit_pkts_refbuf0;

	@@ -129,8 +127,6 @@ static void a5xx_platform_setup(struct adreno_device *adreno_dev)

	static void a5xx_critical_packet_destroy(struct adreno_device *adreno_dev)		static void a5xx_critical_packet_destroy(struct adreno_device *adreno_dev)
	{		{
	kgsl_free_global(&adreno_dev->dev, &crit_pkts);

	kgsl_iommu_unmap_global_secure_pt_entry(KGSL_DEVICE(adreno_dev),		kgsl_iommu_unmap_global_secure_pt_entry(KGSL_DEVICE(adreno_dev),
	&crit_pkts_refbuf0);		&crit_pkts_refbuf0);
	kgsl_sharedmem_free(&crit_pkts_refbuf0);		kgsl_sharedmem_free(&crit_pkts_refbuf0);
	@@ -159,10 +155,10 @@ static int a5xx_critical_packet_construct(struct adreno_device *adreno_dev)
	uint64_t gpuaddrs[4];		uint64_t gpuaddrs[4];
	int ret;		int ret;

	ret = kgsl_allocate_global(&adreno_dev->dev,		adreno_dev->critpkts = kgsl_allocate_global(KGSL_DEVICE(adreno_dev),
	&crit_pkts, PAGE_SIZE * 4, 0, 0, "crit_pkts");		PAGE_SIZE * 4, 0, 0, "crit_pkts");
	if (ret)		if (IS_ERR(adreno_dev->critpkts))
	return ret;		return PTR_ERR(adreno_dev->critpkts);

	ret = kgsl_allocate_user(&adreno_dev->dev, &crit_pkts_refbuf0,		ret = kgsl_allocate_user(&adreno_dev->dev, &crit_pkts_refbuf0,
	PAGE_SIZE, KGSL_MEMFLAGS_SECURE, 0);		PAGE_SIZE, KGSL_MEMFLAGS_SECURE, 0);
	@@ -174,12 +170,12 @@ static int a5xx_critical_packet_construct(struct adreno_device *adreno_dev)
	if (ret)		if (ret)
	return ret;		return ret;

	cmds = crit_pkts.hostptr;		cmds = adreno_dev->critpkts->hostptr;

	gpuaddrs[0] = crit_pkts_refbuf0.gpuaddr;		gpuaddrs[0] = crit_pkts_refbuf0.gpuaddr;
	gpuaddrs[1] = crit_pkts.gpuaddr + PAGE_SIZE;		gpuaddrs[1] = adreno_dev->critpkts->gpuaddr + PAGE_SIZE;
	gpuaddrs[2] = crit_pkts.gpuaddr + (PAGE_SIZE * 2);		gpuaddrs[2] = adreno_dev->critpkts->gpuaddr + (PAGE_SIZE * 2);
	gpuaddrs[3] = crit_pkts.gpuaddr + (PAGE_SIZE * 3);		gpuaddrs[3] = adreno_dev->critpkts->gpuaddr + (PAGE_SIZE * 3);

	crit_pkts_dwords = ARRAY_SIZE(_a5xx_critical_pkts);		crit_pkts_dwords = ARRAY_SIZE(_a5xx_critical_pkts);

	@@ -188,15 +184,15 @@ static int a5xx_critical_packet_construct(struct adreno_device *adreno_dev)
	_do_fixup(critical_pkt_fixups, ARRAY_SIZE(critical_pkt_fixups),		_do_fixup(critical_pkt_fixups, ARRAY_SIZE(critical_pkt_fixups),
	gpuaddrs, cmds);		gpuaddrs, cmds);

	cmds = crit_pkts.hostptr + PAGE_SIZE;		cmds = adreno_dev->critpkts->hostptr + PAGE_SIZE;
	memcpy(cmds, _a5xx_critical_pkts_mem01,		memcpy(cmds, _a5xx_critical_pkts_mem01,
	ARRAY_SIZE(_a5xx_critical_pkts_mem01) << 2);		ARRAY_SIZE(_a5xx_critical_pkts_mem01) << 2);

	cmds = crit_pkts.hostptr + (PAGE_SIZE * 2);		cmds = adreno_dev->critpkts->hostptr + (PAGE_SIZE * 2);
	memcpy(cmds, _a5xx_critical_pkts_mem02,		memcpy(cmds, _a5xx_critical_pkts_mem02,
	ARRAY_SIZE(_a5xx_critical_pkts_mem02) << 2);		ARRAY_SIZE(_a5xx_critical_pkts_mem02) << 2);

	cmds = crit_pkts.hostptr + (PAGE_SIZE * 3);		cmds = adreno_dev->critpkts->hostptr + (PAGE_SIZE * 3);
	memcpy(cmds, _a5xx_critical_pkts_mem03,		memcpy(cmds, _a5xx_critical_pkts_mem03,
	ARRAY_SIZE(_a5xx_critical_pkts_mem03) << 2);		ARRAY_SIZE(_a5xx_critical_pkts_mem03) << 2);

	@@ -1589,7 +1585,7 @@ static int _preemption_init(
	struct kgsl_context *context)		struct kgsl_context *context)
	{		{
	unsigned int *cmds_orig = cmds;		unsigned int *cmds_orig = cmds;
	uint64_t gpuaddr = rb->preemption_desc.gpuaddr;		uint64_t gpuaddr = rb->preemption_desc->gpuaddr;

	/* Turn CP protection OFF */		/* Turn CP protection OFF */
	cmds += cp_protected_mode(adreno_dev, cmds, 0);		cmds += cp_protected_mode(adreno_dev, cmds, 0);
	@@ -1698,13 +1694,13 @@ static int a5xx_microcode_load(struct adreno_device *adreno_dev)
	const struct adreno_a5xx_core *a5xx_core = to_a5xx_core(adreno_dev);		const struct adreno_a5xx_core *a5xx_core = to_a5xx_core(adreno_dev);
	uint64_t gpuaddr;		uint64_t gpuaddr;

	gpuaddr = pm4_fw->memdesc.gpuaddr;		gpuaddr = pm4_fw->memdesc->gpuaddr;
	kgsl_regwrite(device, A5XX_CP_PM4_INSTR_BASE_LO,		kgsl_regwrite(device, A5XX_CP_PM4_INSTR_BASE_LO,
	lower_32_bits(gpuaddr));		lower_32_bits(gpuaddr));
	kgsl_regwrite(device, A5XX_CP_PM4_INSTR_BASE_HI,		kgsl_regwrite(device, A5XX_CP_PM4_INSTR_BASE_HI,
	upper_32_bits(gpuaddr));		upper_32_bits(gpuaddr));

	gpuaddr = pfp_fw->memdesc.gpuaddr;		gpuaddr = pfp_fw->memdesc->gpuaddr;
	kgsl_regwrite(device, A5XX_CP_PFP_INSTR_BASE_LO,		kgsl_regwrite(device, A5XX_CP_PFP_INSTR_BASE_LO,
	lower_32_bits(gpuaddr));		lower_32_bits(gpuaddr));
	kgsl_regwrite(device, A5XX_CP_PFP_INSTR_BASE_HI,		kgsl_regwrite(device, A5XX_CP_PFP_INSTR_BASE_HI,
	@@ -1841,7 +1837,7 @@ int a5xx_critical_packet_submit(struct adreno_device *adreno_dev,
	return PTR_ERR(cmds);		return PTR_ERR(cmds);

	*cmds++ = cp_mem_packet(adreno_dev, CP_INDIRECT_BUFFER_PFE, 2, 1);		*cmds++ = cp_mem_packet(adreno_dev, CP_INDIRECT_BUFFER_PFE, 2, 1);
	cmds += cp_gpuaddr(adreno_dev, cmds, crit_pkts.gpuaddr);		cmds += cp_gpuaddr(adreno_dev, cmds, adreno_dev->critpkts->gpuaddr);
	*cmds++ = crit_pkts_dwords;		*cmds++ = crit_pkts_dwords;

	ret = adreno_ringbuffer_submit_spin(rb, NULL, 20);		ret = adreno_ringbuffer_submit_spin(rb, NULL, 20);
	@@ -1910,7 +1906,7 @@ static int a5xx_rb_start(struct adreno_device *adreno_dev)
	A5XX_CP_RB_CNTL_DEFAULT);		A5XX_CP_RB_CNTL_DEFAULT);

	adreno_writereg64(adreno_dev, ADRENO_REG_CP_RB_BASE,		adreno_writereg64(adreno_dev, ADRENO_REG_CP_RB_BASE,
	ADRENO_REG_CP_RB_BASE_HI, rb->buffer_desc.gpuaddr);		ADRENO_REG_CP_RB_BASE_HI, rb->buffer_desc->gpuaddr);

	ret = a5xx_microcode_load(adreno_dev);		ret = a5xx_microcode_load(adreno_dev);
	if (ret)		if (ret)
	@@ -1937,36 +1933,6 @@ static int a5xx_rb_start(struct adreno_device *adreno_dev)
	return 0;		return 0;
	}		}

	static int _load_firmware(struct kgsl_device device, const char fwfile,
	struct adreno_firmware *firmware)
	{
	const struct firmware *fw = NULL;
	int ret;

	ret = request_firmware(&fw, fwfile, device->dev);

	if (ret) {
	dev_err(device->dev, "request_firmware(%s) failed: %d\n",
	fwfile, ret);
	return ret;
	}

	ret = kgsl_allocate_global(device, &firmware->memdesc, fw->size - 4,
	KGSL_MEMFLAGS_GPUREADONLY, 0, "ucode");

	if (ret)
	goto done;

	memcpy(firmware->memdesc.hostptr, &fw->data[4], fw->size - 4);
	firmware->size = (fw->size - 4) / sizeof(uint32_t);
	firmware->version = (unsigned int )&fw->data[4];

	done:
	release_firmware(fw);

	return ret;
	}

	/*		/*
	* a5xx_microcode_read() - Read microcode		* a5xx_microcode_read() - Read microcode
	* @adreno_dev: Pointer to adreno device		* @adreno_dev: Pointer to adreno device
	@@ -1978,19 +1944,13 @@ static int a5xx_microcode_read(struct adreno_device *adreno_dev)
	struct adreno_firmware *pfp_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PFP);		struct adreno_firmware *pfp_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PFP);
	const struct adreno_a5xx_core *a5xx_core = to_a5xx_core(adreno_dev);		const struct adreno_a5xx_core *a5xx_core = to_a5xx_core(adreno_dev);

	if (pm4_fw->memdesc.hostptr == NULL) {		ret = adreno_get_firmware(adreno_dev, a5xx_core->pm4fw_name, pm4_fw);
	ret = _load_firmware(KGSL_DEVICE(adreno_dev),
	a5xx_core->pm4fw_name, pm4_fw);
	if (ret)		if (ret)
	return ret;		return ret;
	}

	if (pfp_fw->memdesc.hostptr == NULL) {		ret = adreno_get_firmware(adreno_dev, a5xx_core->pfpfw_name, pfp_fw);
	ret = _load_firmware(KGSL_DEVICE(adreno_dev),
	a5xx_core->pfpfw_name, pfp_fw);
	if (ret)		if (ret)
	return ret;		return ret;
	}

	ret = _load_gpmu_firmware(adreno_dev);		ret = _load_gpmu_firmware(adreno_dev);
	if (ret)		if (ret)
	@@ -2665,7 +2625,7 @@ static void a5xx_cp_callback(struct adreno_device *adreno_dev, int bit)
	if (test_bit(ADRENO_DEVICE_CACHE_FLUSH_TS_SUSPENDED, &adreno_dev->priv))		if (test_bit(ADRENO_DEVICE_CACHE_FLUSH_TS_SUSPENDED, &adreno_dev->priv))
	return;		return;

	kgsl_sharedmem_readl(&device->memstore, &cur,		kgsl_sharedmem_readl(device->memstore, &cur,
	KGSL_MEMSTORE_OFFSET(KGSL_MEMSTORE_GLOBAL,		KGSL_MEMSTORE_OFFSET(KGSL_MEMSTORE_GLOBAL,
	ref_wait_ts));		ref_wait_ts));

drivers/gpu/msm/adreno_a5xx_preempt.c

+45 −60

Original line number	Original line	Diff line number	Diff line
	@@ -241,26 +241,26 @@ void a5xx_preemption_trigger(struct adreno_device *adreno_dev)
	* preemption_desc at init time, so no need to check if		* preemption_desc at init time, so no need to check if
	* sharedmem accesses to these memdescs succeed.		* sharedmem accesses to these memdescs succeed.
	*/		*/
	kgsl_sharedmem_readq(&next->pagetable_desc, &ttbr0,		kgsl_sharedmem_readq(next->pagetable_desc, &ttbr0,
	PT_INFO_OFFSET(ttbr0));		PT_INFO_OFFSET(ttbr0));
	kgsl_sharedmem_readl(&next->pagetable_desc, &contextidr,		kgsl_sharedmem_readl(next->pagetable_desc, &contextidr,
	PT_INFO_OFFSET(contextidr));		PT_INFO_OFFSET(contextidr));

	kgsl_sharedmem_writel(device, &next->preemption_desc,		kgsl_sharedmem_writel(device, next->preemption_desc,
	PREEMPT_RECORD(wptr), next->wptr);		PREEMPT_RECORD(wptr), next->wptr);

	spin_unlock_irqrestore(&next->preempt_lock, flags);		spin_unlock_irqrestore(&next->preempt_lock, flags);

	/* And write it to the smmu info */		/* And write it to the smmu info */
	kgsl_sharedmem_writeq(device, &iommu->smmu_info,		kgsl_sharedmem_writeq(device, iommu->smmu_info,
	PREEMPT_SMMU_RECORD(ttbr0), ttbr0);		PREEMPT_SMMU_RECORD(ttbr0), ttbr0);
	kgsl_sharedmem_writel(device, &iommu->smmu_info,		kgsl_sharedmem_writel(device, iommu->smmu_info,
	PREEMPT_SMMU_RECORD(context_idr), contextidr);		PREEMPT_SMMU_RECORD(context_idr), contextidr);

	kgsl_regwrite(device, A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO,		kgsl_regwrite(device, A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO,
	lower_32_bits(next->preemption_desc.gpuaddr));		lower_32_bits(next->preemption_desc->gpuaddr));
	kgsl_regwrite(device, A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI,		kgsl_regwrite(device, A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI,
	upper_32_bits(next->preemption_desc.gpuaddr));		upper_32_bits(next->preemption_desc->gpuaddr));

	adreno_dev->next_rb = next;		adreno_dev->next_rb = next;

	@@ -346,7 +346,7 @@ unsigned int a5xx_preemption_pre_ibsubmit(
	unsigned int cmds, struct kgsl_context context)		unsigned int cmds, struct kgsl_context context)
	{		{
	unsigned int *cmds_orig = cmds;		unsigned int *cmds_orig = cmds;
	uint64_t gpuaddr = rb->preemption_desc.gpuaddr;		uint64_t gpuaddr = rb->preemption_desc->gpuaddr;
	unsigned int preempt_style = 0;		unsigned int preempt_style = 0;

	if (context) {		if (context) {
	@@ -463,31 +463,31 @@ void a5xx_preemption_start(struct adreno_device *adreno_dev)
	adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_NONE);		adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_NONE);

	/* smmu_info is allocated and mapped in a5xx_preemption_iommu_init */		/* smmu_info is allocated and mapped in a5xx_preemption_iommu_init */
	kgsl_sharedmem_writel(device, &iommu->smmu_info,		kgsl_sharedmem_writel(device, iommu->smmu_info,
	PREEMPT_SMMU_RECORD(magic), A5XX_CP_SMMU_INFO_MAGIC_REF);		PREEMPT_SMMU_RECORD(magic), A5XX_CP_SMMU_INFO_MAGIC_REF);
	kgsl_sharedmem_writeq(device, &iommu->smmu_info,		kgsl_sharedmem_writeq(device, iommu->smmu_info,
	PREEMPT_SMMU_RECORD(ttbr0), MMU_DEFAULT_TTBR0(device));		PREEMPT_SMMU_RECORD(ttbr0), MMU_DEFAULT_TTBR0(device));

	/* The CP doesn't use the asid record, so poison it */		/* The CP doesn't use the asid record, so poison it */
	kgsl_sharedmem_writel(device, &iommu->smmu_info,		kgsl_sharedmem_writel(device, iommu->smmu_info,
	PREEMPT_SMMU_RECORD(asid), 0xDECAFBAD);		PREEMPT_SMMU_RECORD(asid), 0xDECAFBAD);
	kgsl_sharedmem_writel(device, &iommu->smmu_info,		kgsl_sharedmem_writel(device, iommu->smmu_info,
	PREEMPT_SMMU_RECORD(context_idr),		PREEMPT_SMMU_RECORD(context_idr),
	MMU_DEFAULT_CONTEXTIDR(device));		MMU_DEFAULT_CONTEXTIDR(device));

	adreno_writereg64(adreno_dev,		adreno_writereg64(adreno_dev,
	ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_LO,		ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_LO,
	ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_HI,		ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_HI,
	iommu->smmu_info.gpuaddr);		iommu->smmu_info->gpuaddr);

	FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {		FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {
	/*		/*
	* preemption_desc is allocated and mapped at init time,		* preemption_desc is allocated and mapped at init time,
	* so no need to check sharedmem_writel return value		* so no need to check sharedmem_writel return value
	*/		*/
	kgsl_sharedmem_writel(device, &rb->preemption_desc,		kgsl_sharedmem_writel(device, rb->preemption_desc,
	PREEMPT_RECORD(rptr), 0);		PREEMPT_RECORD(rptr), 0);
	kgsl_sharedmem_writel(device, &rb->preemption_desc,		kgsl_sharedmem_writel(device, rb->preemption_desc,
	PREEMPT_RECORD(wptr), 0);		PREEMPT_RECORD(wptr), 0);

	adreno_ringbuffer_set_pagetable(rb,		adreno_ringbuffer_set_pagetable(rb,
	@@ -500,32 +500,33 @@ static int a5xx_preemption_ringbuffer_init(struct adreno_device *adreno_dev,
	struct adreno_ringbuffer *rb, uint64_t counteraddr)		struct adreno_ringbuffer *rb, uint64_t counteraddr)
	{		{
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
	int ret;

	ret = kgsl_allocate_global(device, &rb->preemption_desc,		if (IS_ERR_OR_NULL(rb->preemption_desc))
	A5XX_CP_CTXRECORD_SIZE_IN_BYTES, 0, KGSL_MEMDESC_PRIVILEGED,		rb->preemption_desc = kgsl_allocate_global(device,
	"preemption_desc");		A5XX_CP_CTXRECORD_SIZE_IN_BYTES, 0,
	if (ret)		KGSL_MEMDESC_PRIVILEGED, "preemption_desc");
	return ret;

	kgsl_sharedmem_writel(device, &rb->preemption_desc,		if (IS_ERR(rb->preemption_desc))
			return PTR_ERR(rb->preemption_desc);

			kgsl_sharedmem_writel(device, rb->preemption_desc,
	PREEMPT_RECORD(magic), A5XX_CP_CTXRECORD_MAGIC_REF);		PREEMPT_RECORD(magic), A5XX_CP_CTXRECORD_MAGIC_REF);
	kgsl_sharedmem_writel(device, &rb->preemption_desc,		kgsl_sharedmem_writel(device, rb->preemption_desc,
	PREEMPT_RECORD(info), 0);		PREEMPT_RECORD(info), 0);
	kgsl_sharedmem_writel(device, &rb->preemption_desc,		kgsl_sharedmem_writel(device, rb->preemption_desc,
	PREEMPT_RECORD(data), 0);		PREEMPT_RECORD(data), 0);
	kgsl_sharedmem_writel(device, &rb->preemption_desc,		kgsl_sharedmem_writel(device, rb->preemption_desc,
	PREEMPT_RECORD(cntl), A5XX_CP_RB_CNTL_DEFAULT);		PREEMPT_RECORD(cntl), A5XX_CP_RB_CNTL_DEFAULT);
	kgsl_sharedmem_writel(device, &rb->preemption_desc,		kgsl_sharedmem_writel(device, rb->preemption_desc,
	PREEMPT_RECORD(rptr), 0);		PREEMPT_RECORD(rptr), 0);
	kgsl_sharedmem_writel(device, &rb->preemption_desc,		kgsl_sharedmem_writel(device, rb->preemption_desc,
	PREEMPT_RECORD(wptr), 0);		PREEMPT_RECORD(wptr), 0);
	kgsl_sharedmem_writeq(device, &rb->preemption_desc,		kgsl_sharedmem_writeq(device, rb->preemption_desc,
	PREEMPT_RECORD(rptr_addr), SCRATCH_RPTR_GPU_ADDR(device,		PREEMPT_RECORD(rptr_addr), SCRATCH_RPTR_GPU_ADDR(device,
	rb->id));		rb->id));
	kgsl_sharedmem_writeq(device, &rb->preemption_desc,		kgsl_sharedmem_writeq(device, rb->preemption_desc,
	PREEMPT_RECORD(rbase), rb->buffer_desc.gpuaddr);		PREEMPT_RECORD(rbase), rb->buffer_desc->gpuaddr);
	kgsl_sharedmem_writeq(device, &rb->preemption_desc,		kgsl_sharedmem_writeq(device, rb->preemption_desc,
	PREEMPT_RECORD(counter), counteraddr);		PREEMPT_RECORD(counter), counteraddr);

	return 0;		return 0;
	@@ -538,44 +539,25 @@ static int a5xx_preemption_iommu_init(struct adreno_device *adreno_dev)
	struct kgsl_iommu *iommu = KGSL_IOMMU_PRIV(device);		struct kgsl_iommu *iommu = KGSL_IOMMU_PRIV(device);

	/* Allocate mem for storing preemption smmu record */		/* Allocate mem for storing preemption smmu record */
	return kgsl_allocate_global(device, &iommu->smmu_info, PAGE_SIZE,		if (IS_ERR_OR_NULL(iommu->smmu_info))
			iommu->smmu_info = kgsl_allocate_global(device, PAGE_SIZE,
	KGSL_MEMFLAGS_GPUREADONLY, KGSL_MEMDESC_PRIVILEGED,		KGSL_MEMFLAGS_GPUREADONLY, KGSL_MEMDESC_PRIVILEGED,
	"smmu_info");		"smmu_info");
	}

	static void a5xx_preemption_iommu_close(struct adreno_device *adreno_dev)		return PTR_ERR_OR_ZERO(iommu->smmu_info);
	{
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
	struct kgsl_iommu *iommu = KGSL_IOMMU_PRIV(device);

	kgsl_free_global(device, &iommu->smmu_info);
	}		}

	#else		#else
	static int a5xx_preemption_iommu_init(struct adreno_device *adreno_dev)		static int a5xx_preemption_iommu_init(struct adreno_device *adreno_dev)
	{		{
	return -ENODEV;		return -ENODEV;
	}		}

	static void a5xx_preemption_iommu_close(struct adreno_device *adreno_dev)
	{
	}
	#endif		#endif

	static void _preemption_close(struct adreno_device *adreno_dev)		static void _preemption_close(struct adreno_device *adreno_dev)
	{		{
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
	struct adreno_preemption *preempt = &adreno_dev->preempt;		struct adreno_preemption *preempt = &adreno_dev->preempt;
	struct adreno_ringbuffer *rb;
	unsigned int i;

	del_timer(&preempt->timer);		del_timer(&preempt->timer);
	kgsl_free_global(device, &preempt->counters);
	a5xx_preemption_iommu_close(adreno_dev);

	FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {
	kgsl_free_global(device, &rb->preemption_desc);
	}
	}		}

	void a5xx_preemption_close(struct adreno_device *adreno_dev)		void a5xx_preemption_close(struct adreno_device *adreno_dev)
	@@ -604,14 +586,17 @@ int a5xx_preemption_init(struct adreno_device *adreno_dev)
	timer_setup(&preempt->timer, _a5xx_preemption_timer, 0);		timer_setup(&preempt->timer, _a5xx_preemption_timer, 0);

	/* Allocate mem for storing preemption counters */		/* Allocate mem for storing preemption counters */
	ret = kgsl_allocate_global(device, &preempt->counters,		if (IS_ERR_OR_NULL(preempt->counters))
			preempt->counters = kgsl_allocate_global(device,
	adreno_dev->num_ringbuffers *		adreno_dev->num_ringbuffers *
	A5XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE, 0, 0,		A5XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE, 0, 0,
	"preemption_counters");		"preemption_counters");

			ret = PTR_ERR_OR_ZERO(preempt->counters);
	if (ret)		if (ret)
	goto err;		goto err;

	addr = preempt->counters.gpuaddr;		addr = preempt->counters->gpuaddr;

	/* Allocate mem for storing preemption switch record */		/* Allocate mem for storing preemption switch record */
	FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {		FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {