Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2f20b6b8 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "bindings: clock: qcom: Update the GPU CC clock IDs"

parents 36c4e045 fbf704a3

drivers/clk/qcom/clk-branch.c

+58 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2013, 2016-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2013, 2016-2020, The Linux Foundation. All rights reserved.

 */



#include <linux/kernel.h>
@@ -11,6 +11,7 @@ 
#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/regmap.h>

#include <linux/clk/qcom.h>



#include "clk-branch.h"

#include "clk-debug.h"
@@ -199,6 +200,10 @@ static void clk_branch2_init(struct clk_hw *hw) 
}



const struct clk_ops clk_branch2_ops = {

	.prepare = clk_prepare_regmap,

	.unprepare = clk_unprepare_regmap,

	.pre_rate_change = clk_pre_change_regmap,

	.post_rate_change = clk_post_change_regmap,

	.enable = clk_branch2_enable,

	.disable = clk_branch2_disable,

	.is_enabled = clk_is_enabled_regmap,
@@ -272,3 +277,55 @@ const struct clk_ops clk_branch_simple_ops = { 
	.is_enabled = clk_is_enabled_regmap,

};

EXPORT_SYMBOL_GPL(clk_branch_simple_ops);



int qcom_clk_set_flags(struct clk *clk, unsigned long flags)

{

	struct clk_hw *hw;

	struct clk_branch *br;

	u32 cbcr_val = 0, cbcr_mask;

	int ret;



	if (IS_ERR_OR_NULL(clk))

		return 0;



	hw = __clk_get_hw(clk);

	if (IS_ERR_OR_NULL(hw))

		return -EINVAL;



	switch (flags) {

	case CLKFLAG_PERIPH_OFF_SET:

		cbcr_val = cbcr_mask = BIT(12);

		break;

	case CLKFLAG_PERIPH_OFF_CLEAR:

		cbcr_mask = BIT(12);

		break;

	case CLKFLAG_RETAIN_PERIPH:

		cbcr_val = cbcr_mask = BIT(13);

		break;

	case CLKFLAG_NORETAIN_PERIPH:

		cbcr_mask = BIT(13);

		break;

	case CLKFLAG_RETAIN_MEM:

		cbcr_val = cbcr_mask = BIT(14);

		break;

	case CLKFLAG_NORETAIN_MEM:

		cbcr_mask = BIT(14);

		break;

	default:

		return -EINVAL;

	}



	br = to_clk_branch(hw);

	ret = regmap_update_bits(br->clkr.regmap, br->halt_reg, cbcr_mask,

								cbcr_val);

	if (ret)

		return ret;



	/* Make sure power is enabled/disabled before returning. */

	mb();



	udelay(1);



	return 0;

}

EXPORT_SYMBOL(qcom_clk_set_flags);

include/dt-bindings/clock/qcom,gpucc-holi.h

+17 −31
Original line number Diff line number Diff line
@@ -9,36 +9,22 @@ 
/* GPU_CC clocks */

#define GPU_CC_PLL0						0

#define GPU_CC_PLL1						1

#define GPU_CC_ACD_AHB_CLK			2

#define GPU_CC_ACD_CXO_CLK			3

#define GPU_CC_AHB_CLK				4

#define GPU_CC_CRC_AHB_CLK			5

#define GPU_CC_CX_APB_CLK			6

#define GPU_CC_CX_GFX3D_CLK			7

#define GPU_CC_CX_GFX3D_SLV_CLK			8

#define GPU_CC_CX_GMU_CLK			9

#define GPU_CC_CX_SNOC_DVM_CLK			10

#define GPU_CC_CXO_AON_CLK			11

#define GPU_CC_CXO_CLK				12

#define GPU_CC_GMU_CLK_SRC			13

#define GPU_CC_GX_CXO_CLK			14

#define GPU_CC_GX_GFX3D_CLK			15

#define GPU_CC_GX_GMU_CLK			16

#define GPU_CC_GX_QDSS_TSCTR_CLK		17

#define GPU_CC_GX_VSENSE_CLK			18

#define GPU_CC_SLEEP_CLK			19

#define GPU_CC_AHB_CLK						2

#define GPU_CC_CX_GFX3D_CLK					3

#define GPU_CC_CX_GFX3D_SLV_CLK					4

#define GPU_CC_CX_GMU_CLK					5

#define GPU_CC_CX_SNOC_DVM_CLK					6

#define GPU_CC_CXO_AON_CLK					7

#define GPU_CC_CXO_CLK						8

#define GPU_CC_GMU_CLK_SRC					9

#define GPU_CC_GX_CXO_CLK					10

#define GPU_CC_GX_GFX3D_CLK					11

#define GPU_CC_GX_GFX3D_CLK_SRC					12

#define GPU_CC_GX_GMU_CLK					13

#define GPU_CC_SLEEP_CLK					14



/* GPU_CC power domains */

#define CX_GDSC							0

#define GX_GDSC							1



/* GPU_CC resets */

#define GPUCC_GPU_CC_ACD_BCR			0

#define GPUCC_GPU_CC_CX_BCR			1

#define GPUCC_GPU_CC_GFX3D_AON_BCR		2

#define GPUCC_GPU_CC_GMU_BCR			3

#define GPUCC_GPU_CC_GX_BCR			4

#define GPUCC_GPU_CC_RBCPR_BCR			5

#define GPUCC_GPU_CC_XO_BCR			6



#endif

include/linux/clk/qcom.h

+11 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2020 The Linux Foundation. All rights reserved.

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 */



#ifndef __LINUX_CLK_QCOM_H_
@@ -8,6 +8,16 @@ 


#include <linux/clk-provider.h>



enum branch_mem_flags {

	CLKFLAG_RETAIN_PERIPH,

	CLKFLAG_NORETAIN_PERIPH,

	CLKFLAG_RETAIN_MEM,

	CLKFLAG_NORETAIN_MEM,

	CLKFLAG_PERIPH_OFF_SET,

	CLKFLAG_PERIPH_OFF_CLEAR,

};



int qcom_clk_get_voltage(struct clk *clk, unsigned long rate);

int qcom_clk_set_flags(struct clk *clk, unsigned long flags);



#endif  /* __LINUX_CLK_QCOM_H_ */