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Commit 2ef7b45a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://github.com/davem330/net 

* git://github.com/davem330/net:
  ipv6-multicast: Fix memory leak in IPv6 multicast.
  ipv6: check return value for dst_alloc
  net: check return value for dst_alloc
  ipv6-multicast: Fix memory leak in input path.
  bnx2x: add missing break in bnx2x_dcbnl_get_cap
  bnx2x: fix WOL by enablement PME in config space
  bnx2x: fix hw attention handling
  net: fix a typo in Documentation/networking/scaling.txt
  ath9k: Fix a dma warning/memory leak
  rtlwifi: rtl8192cu: Fix unitialized struct
  iwlagn: fix dangling scan request
  batman-adv: do_bcast has to be true for broadcast packets only
  cfg80211: Fix validation of AKM suites
  iwlegacy: do not use interruptible waits
  iwlegacy: fix command queue timeout
  ath9k_hw: Fix Rx DMA stuck for AR9003 chips
parents 07117e30 b582ad8e

Documentation/networking/scaling.txt

+1 −1
Original line number Diff line number Diff line
@@ -243,7 +243,7 @@ configured. The number of entries in the global flow table is set through: 


The number of entries in the per-queue flow table are set through:



 /sys/class/net/<dev>/queues/tx-<n>/rps_flow_cnt

 /sys/class/net/<dev>/queues/rx-<n>/rps_flow_cnt



== Suggested Configuration

drivers/net/bnx2x/bnx2x_dcb.c

+1 −0
Original line number Diff line number Diff line
@@ -2120,6 +2120,7 @@ static u8 bnx2x_dcbnl_get_cap(struct net_device *netdev, int capid, u8 *cap) 
			break;

		case DCB_CAP_ATTR_DCBX:

			*cap = BNX2X_DCBX_CAPS;

			break;

		default:

			rval = -EINVAL;

			break;

drivers/net/bnx2x/bnx2x_main.c

+13 −3
Original line number Diff line number Diff line
@@ -4943,7 +4943,7 @@ static void bnx2x_init_def_sb(struct bnx2x *bp) 
	int igu_seg_id;

	int port = BP_PORT(bp);

	int func = BP_FUNC(bp);

	int reg_offset;

	int reg_offset, reg_offset_en5;

	u64 section;

	int index;

	struct hc_sp_status_block_data sp_sb_data;
@@ -4966,6 +4966,8 @@ static void bnx2x_init_def_sb(struct bnx2x *bp) 


	reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :

			     MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);

	reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :

				 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);

	for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {

		int sindex;

		/* take care of sig[0]..sig[4] */
@@ -4980,7 +4982,7 @@ static void bnx2x_init_def_sb(struct bnx2x *bp) 
			 * and not 16 between the different groups

			 */

			bp->attn_group[index].sig[4] = REG_RD(bp,

					reg_offset + 0x10 + 0x4*index);

					reg_offset_en5 + 0x4*index);

		else

			bp->attn_group[index].sig[4] = 0;

	}
@@ -7625,8 +7627,11 @@ u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 
		u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;

		u8 *mac_addr = bp->dev->dev_addr;

		u32 val;

		u16 pmc;



		/* The mac address is written to entries 1-4 to

		   preserve entry 0 which is used by the PMF */

		 * preserve entry 0 which is used by the PMF

		 */

		u8 entry = (BP_VN(bp) + 1)*8;



		val = (mac_addr[0] << 8) | mac_addr[1];
@@ -7636,6 +7641,11 @@ u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 
		      (mac_addr[4] << 8) | mac_addr[5];

		EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);



		/* Enable the PME and clear the status */

		pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);

		pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;

		pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);



		reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;



	} else

drivers/net/bnx2x/bnx2x_reg.h

+12 −0
Original line number Diff line number Diff line
@@ -1384,6 +1384,18 @@ 
   Latched ump_tx_parity; [31] MCP Latched scpad_parity; */

#define MISC_REG_AEU_ENABLE4_PXP_0				 0xa108

#define MISC_REG_AEU_ENABLE4_PXP_1				 0xa1a8

/* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped

 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC

 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]

 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1

 * parity; [31-10] Reserved; */

#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0			 0xa688

/* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped

 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC

 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]

 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1

 * parity; [31-10] Reserved; */

#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0			 0xa6b0

/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu

   128 bit vector */

#define MISC_REG_AEU_GENERAL_ATTN_0				 0xa000

drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h

+1 −1
Original line number Diff line number Diff line
@@ -1514,7 +1514,7 @@ static const u32 ar9300_2p2_mac_core[][2] = { 
	{0x00008258, 0x00000000},

	{0x0000825c, 0x40000000},

	{0x00008260, 0x00080922},

	{0x00008264, 0x9bc00010},

	{0x00008264, 0x9d400010},

	{0x00008268, 0xffffffff},

	{0x0000826c, 0x0000ffff},

	{0x00008270, 0x00000000},