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Commit 2ee936e3 authored by José Roberto de Souza's avatar José Roberto de Souza
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drm/i915/psr: Move intel_psr_disable_source() code to intel_psr_disable_locked() 



In the past we had hooks to configure HW for VLV/CHV too, in the drop
of VLV/CHV support the intel_psr_disable_source() code was not moved
to the caller, so doing it here.

Suggested-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181106190843.18009-4-jose.souza@intel.com
parent 62819dfd

drivers/gpu/drm/i915/intel_psr.c

+9 −16
Original line number Diff line number Diff line
@@ -680,13 +680,20 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv) 
	dev_priv->psr.active = false;

}



static void

intel_psr_disable_source(struct intel_dp *intel_dp)

static void intel_psr_disable_locked(struct intel_dp *intel_dp)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	i915_reg_t psr_status;

	u32 psr_status_mask;



	lockdep_assert_held(&dev_priv->psr.lock);



	if (!dev_priv->psr.enabled)

		return;



	DRM_DEBUG_KMS("Disabling PSR%s\n",

		      dev_priv->psr.psr2_enabled ? "2" : "1");



	intel_psr_exit(dev_priv);



	if (dev_priv->psr.psr2_enabled) {
@@ -701,20 +708,6 @@ intel_psr_disable_source(struct intel_dp *intel_dp) 
	if (intel_wait_for_register(dev_priv, psr_status, psr_status_mask, 0,

				    2000))

		DRM_ERROR("Timed out waiting PSR idle state\n");

}



static void intel_psr_disable_locked(struct intel_dp *intel_dp)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);



	lockdep_assert_held(&dev_priv->psr.lock);



	if (!dev_priv->psr.enabled)

		return;



	DRM_DEBUG_KMS("Disabling PSR%s\n",

		      dev_priv->psr.psr2_enabled ? "2" : "1");

	intel_psr_disable_source(intel_dp);



	/* Disable PSR on Sink */

	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);