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Commit 2ecedc47 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "Nothing major in here, one radeon SI fix for tiling, and one uninit
  var fix, two minor header file fixes."

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm: drop comment about this header being autogenerated.
  drm/edid: don't return stack garbage from supports_rb
  vga_switcheroo: Add include guard
  drm/radeon: SI tiling fixes for display
parents 002b758b 59bbe27b

drivers/gpu/drm/drm_edid.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -610,7 +610,7 @@ static bool 
drm_monitor_supports_rb(struct edid *edid)

drm_monitor_supports_rb(struct edid *edid)

{

{

	if (edid->revision >= 4) {

	if (edid->revision >= 4) {

		bool ret;

		bool ret = false;

		drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);

		drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);

		return ret;

		return ret;

	}

	}

drivers/gpu/drm/radeon/atombios_crtc.c

+9 −1
Original line number Original line Diff line number Diff line
@@ -1149,7 +1149,9 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 
	}

	}





	if (tiling_flags & RADEON_TILING_MACRO) {

	if (tiling_flags & RADEON_TILING_MACRO) {

		if (rdev->family >= CHIP_CAYMAN)

		if (rdev->family >= CHIP_TAHITI)

			tmp = rdev->config.si.tile_config;

		else if (rdev->family >= CHIP_CAYMAN)

			tmp = rdev->config.cayman.tile_config;

			tmp = rdev->config.cayman.tile_config;

		else

		else

			tmp = rdev->config.evergreen.tile_config;

			tmp = rdev->config.evergreen.tile_config;
@@ -1177,6 +1179,12 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 
	} else if (tiling_flags & RADEON_TILING_MICRO)

	} else if (tiling_flags & RADEON_TILING_MICRO)

		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);

		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);





	if ((rdev->family == CHIP_TAHITI) ||

	    (rdev->family == CHIP_PITCAIRN))

		fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);

	else if (rdev->family == CHIP_VERDE)

		fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);



	switch (radeon_crtc->crtc_id) {

	switch (radeon_crtc->crtc_id) {

	case 0:

	case 0:

		WREG32(AVIVO_D1VGA_CONTROL, 0);

		WREG32(AVIVO_D1VGA_CONTROL, 0);

drivers/gpu/drm/radeon/si_reg.h

+72 −0
Original line number Original line Diff line number Diff line
@@ -30,4 +30,76 @@ 
#define SI_DC_GPIO_HPD_EN                        0x65b8

#define SI_DC_GPIO_HPD_EN                        0x65b8

#define SI_DC_GPIO_HPD_Y                         0x65bc

#define SI_DC_GPIO_HPD_Y                         0x65bc





#define SI_GRPH_CONTROL                          0x6804

#       define SI_GRPH_DEPTH(x)                  (((x) & 0x3) << 0)

#       define SI_GRPH_DEPTH_8BPP                0

#       define SI_GRPH_DEPTH_16BPP               1

#       define SI_GRPH_DEPTH_32BPP               2

#       define SI_GRPH_NUM_BANKS(x)              (((x) & 0x3) << 2)

#       define SI_ADDR_SURF_2_BANK               0

#       define SI_ADDR_SURF_4_BANK               1

#       define SI_ADDR_SURF_8_BANK               2

#       define SI_ADDR_SURF_16_BANK              3

#       define SI_GRPH_Z(x)                      (((x) & 0x3) << 4)

#       define SI_GRPH_BANK_WIDTH(x)             (((x) & 0x3) << 6)

#       define SI_ADDR_SURF_BANK_WIDTH_1         0

#       define SI_ADDR_SURF_BANK_WIDTH_2         1

#       define SI_ADDR_SURF_BANK_WIDTH_4         2

#       define SI_ADDR_SURF_BANK_WIDTH_8         3

#       define SI_GRPH_FORMAT(x)                 (((x) & 0x7) << 8)

/* 8 BPP */

#       define SI_GRPH_FORMAT_INDEXED            0

/* 16 BPP */

#       define SI_GRPH_FORMAT_ARGB1555           0

#       define SI_GRPH_FORMAT_ARGB565            1

#       define SI_GRPH_FORMAT_ARGB4444           2

#       define SI_GRPH_FORMAT_AI88               3

#       define SI_GRPH_FORMAT_MONO16             4

#       define SI_GRPH_FORMAT_BGRA5551           5

/* 32 BPP */

#       define SI_GRPH_FORMAT_ARGB8888           0

#       define SI_GRPH_FORMAT_ARGB2101010        1

#       define SI_GRPH_FORMAT_32BPP_DIG          2

#       define SI_GRPH_FORMAT_8B_ARGB2101010     3

#       define SI_GRPH_FORMAT_BGRA1010102        4

#       define SI_GRPH_FORMAT_8B_BGRA1010102     5

#       define SI_GRPH_FORMAT_RGB111110          6

#       define SI_GRPH_FORMAT_BGR101111          7

#       define SI_GRPH_BANK_HEIGHT(x)            (((x) & 0x3) << 11)

#       define SI_ADDR_SURF_BANK_HEIGHT_1        0

#       define SI_ADDR_SURF_BANK_HEIGHT_2        1

#       define SI_ADDR_SURF_BANK_HEIGHT_4        2

#       define SI_ADDR_SURF_BANK_HEIGHT_8        3

#       define SI_GRPH_TILE_SPLIT(x)             (((x) & 0x7) << 13)

#       define SI_ADDR_SURF_TILE_SPLIT_64B       0

#       define SI_ADDR_SURF_TILE_SPLIT_128B      1

#       define SI_ADDR_SURF_TILE_SPLIT_256B      2

#       define SI_ADDR_SURF_TILE_SPLIT_512B      3

#       define SI_ADDR_SURF_TILE_SPLIT_1KB       4

#       define SI_ADDR_SURF_TILE_SPLIT_2KB       5

#       define SI_ADDR_SURF_TILE_SPLIT_4KB       6

#       define SI_GRPH_MACRO_TILE_ASPECT(x)      (((x) & 0x3) << 18)

#       define SI_ADDR_SURF_MACRO_TILE_ASPECT_1  0

#       define SI_ADDR_SURF_MACRO_TILE_ASPECT_2  1

#       define SI_ADDR_SURF_MACRO_TILE_ASPECT_4  2

#       define SI_ADDR_SURF_MACRO_TILE_ASPECT_8  3

#       define SI_GRPH_ARRAY_MODE(x)             (((x) & 0x7) << 20)

#       define SI_GRPH_ARRAY_LINEAR_GENERAL      0

#       define SI_GRPH_ARRAY_LINEAR_ALIGNED      1

#       define SI_GRPH_ARRAY_1D_TILED_THIN1      2

#       define SI_GRPH_ARRAY_2D_TILED_THIN1      4

#       define SI_GRPH_PIPE_CONFIG(x)		 (((x) & 0x1f) << 24)

#       define SI_ADDR_SURF_P2			 0

#       define SI_ADDR_SURF_P4_8x16		 4

#       define SI_ADDR_SURF_P4_16x16		 5

#       define SI_ADDR_SURF_P4_16x32		 6

#       define SI_ADDR_SURF_P4_32x32		 7

#       define SI_ADDR_SURF_P8_16x16_8x16	 8

#       define SI_ADDR_SURF_P8_16x32_8x16	 9

#       define SI_ADDR_SURF_P8_32x32_8x16	 10

#       define SI_ADDR_SURF_P8_16x32_16x16	 11

#       define SI_ADDR_SURF_P8_32x32_16x16	 12

#       define SI_ADDR_SURF_P8_32x32_16x32	 13

#       define SI_ADDR_SURF_P8_32x64_32x32	 14



#endif
 
#endif

include/drm/drm_pciids.h

+0 −4
Original line number Original line Diff line number Diff line 
/*

   This file is auto-generated from the drm_pciids.txt in the DRM CVS

   Please contact dri-devel@lists.sf.net to add new cards to this list

*/

#define radeon_PCI_IDS \

#define radeon_PCI_IDS \

	{0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \

	{0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \

	{0x1002, 0x3151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \

	{0x1002, 0x3151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \

include/linux/vga_switcheroo.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -7,6 +7,9 @@ 
 * vga_switcheroo.h - Support for laptop with dual GPU using one set of outputs

 * vga_switcheroo.h - Support for laptop with dual GPU using one set of outputs

 */

 */





#ifndef _LINUX_VGA_SWITCHEROO_H_

#define _LINUX_VGA_SWITCHEROO_H_



#include <linux/fb.h>

#include <linux/fb.h>





struct pci_dev;

struct pci_dev;
@@ -73,3 +76,4 @@ static inline int vga_switcheroo_get_client_state(struct pci_dev *dev) { return 








#endif

#endif

#endif /* _LINUX_VGA_SWITCHEROO_H_ */