Merge branch 'spi-5.2' into spi-next

- gpios : specifies the gpio pins to be used for chipselects.

  The gpios will be referred to as reg = <index> in the SPI child nodes.

  If unspecified, a single SPI device without a chip select can be used.

- fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the

  SPISEL_BOOT signal is used as chip select for a slave device. Use

  reg = <number of gpios> in the corresponding child node, i.e. 0 if

  the gpios property is not present.

Example:

	spi@4c0 {

Recommended properties:

- spi-max-frequency: Definition as per

                     Documentation/devicetree/bindings/spi/spi-bus.txt

Optional properties:

- nvidia,tx-clk-tap-delay: Delays the clock going out to the external device

  with this tap value. This property is used to tune the outgoing data from

  Tegra SPI master with respect to outgoing Tegra SPI master clock.

  Tap values vary based on the platform design trace lengths from Tegra SPI

  to corresponding slave devices. Valid tap values are from 0 thru 63.

- nvidia,rx-clk-tap-delay: Delays the clock coming in from the external device

  with this tap value. This property is used to adjust the Tegra SPI master

  clock with respect to the data from the SPI slave device.

  Tap values vary based on the platform design trace lengths from Tegra SPI

  to corresponding slave devices. Valid tap values are from 0 thru 63.

Example:

spi@7000d600 {

	reset-names = "spi";

	dmas = <&apbdma 16>, <&apbdma 16>;

	dma-names = "rx", "tx";

	<spi-client>@<bus_num> {

		...

		...

		nvidia,rx-clk-tap-delay = <0>;

		nvidia,tx-clk-tap-delay = <16>;

		...

	};

};

- compatible           : "renesas,msiof-r8a7743" (RZ/G1M)

			 "renesas,msiof-r8a7744" (RZ/G1N)

			 "renesas,msiof-r8a7745" (RZ/G1E)

			 "renesas,msiof-r8a77470" (RZ/G1C)

			 "renesas,msiof-r8a774a1" (RZ/G2M)

			 "renesas,msiof-r8a774c0" (RZ/G2E)

			 "renesas,msiof-r8a7790" (R-Car H2)

- interrupts : One interrupt, used by the controller.

- #address-cells : <1>, as required by generic SPI binding.

- #size-cells : <0>, also as required by generic SPI binding.

- clocks : phandles for the clocks, see the description of clock-names below.

   The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock

   is optional. If a single clock is specified but no clock-name, it is the

   "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.

Optional properties:

- cs-gpios : Specifies the gpio pis to be used for chipselects.

- clock-names : Contains the names of the clocks:

    "ssi_clk", for the core clock used to generate the external SPI clock.

    "pclk", the interface clock, required for register access.

- cs-gpios : Specifies the gpio pins to be used for chipselects.

- num-cs : The number of chipselects. If omitted, this will default to 4.

- reg-io-width : The I/O register width (in bytes) implemented by this

  device.  Supported values are 2 or 4 (the default).

		interrupts = <0 154 4>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&spi_m_clk>;

		num-cs = <2>;

		cs-gpios = <&gpio0 13 0>,

			   <&gpio0 14 0>;

- reg : address and length of the lpspi master registers

- interrupt-parent : core interrupt controller

- interrupts : lpspi interrupt

- clocks : lpspi clock specifier

- clocks : lpspi clock specifier. Its number and order need to correspond to the

	   value in clock-names.

- clock-names : Corresponding to per clock and ipg clock in "clocks"

		respectively. In i.MX7ULP, it only has per clk, so use CLK_DUMMY

		to fill the "ipg" blank.

- spi-slave : spi slave mode support. In slave mode, add this attribute without

	      value. In master mode, remove it.

	reg = <0x40290000 0x10000>;

	interrupt-parent = <&intc>;

	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&clks IMX7ULP_CLK_LPSPI2>;

	clocks = <&clks IMX7ULP_CLK_LPSPI2>,

		 <&clks IMX7ULP_CLK_DUMMY>;

	clock-names = "per", "ipg";

	spi-slave;

};