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Commit 2e523e98 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Implement chv display PHY lane stagger setup 



Set up the chv display PHY lane stagger registers according to
"Programming Guide for 1273 CHV eDP/DP/HDMI Display PHY" v1.04

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarDeepak S <deepak.s@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ac935a8b

drivers/gpu/drm/i915/i915_reg.h

+13 −0
Original line number Diff line number Diff line
@@ -961,6 +961,7 @@ enum skl_disp_power_wells { 


#define _VLV_PCS_DW11_CH0		0x822c

#define _VLV_PCS_DW11_CH1		0x842c

#define   DPIO_TX2_STAGGER_MASK(x)	((x)<<24)

#define   DPIO_LANEDESKEW_STRAP_OVRD	(1<<3)

#define   DPIO_LEFT_TXFIFO_RST_MASTER	(1<<1)

#define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1<<0)
@@ -973,8 +974,20 @@ enum skl_disp_power_wells { 
#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)

#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)



#define _VLV_PCS01_DW12_CH0		0x0230

#define _VLV_PCS23_DW12_CH0		0x0430

#define _VLV_PCS01_DW12_CH1		0x2630

#define _VLV_PCS23_DW12_CH1		0x2830

#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)

#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)



#define _VLV_PCS_DW12_CH0		0x8230

#define _VLV_PCS_DW12_CH1		0x8430

#define   DPIO_TX2_STAGGER_MULT(x)	((x)<<20)

#define   DPIO_TX1_STAGGER_MULT(x)	((x)<<16)

#define   DPIO_TX1_STAGGER_MASK(x)	((x)<<8)

#define   DPIO_LANESTAGGER_STRAP_OVRD	(1<<6)

#define   DPIO_LANESTAGGER_STRAP(x)	((x)<<0)

#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)



#define _VLV_PCS_DW14_CH0		0x8238

drivers/gpu/drm/i915/intel_dp.c

+33 −2
Original line number Diff line number Diff line
@@ -2732,7 +2732,7 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder) 
		to_intel_crtc(encoder->base.crtc);

	enum dpio_channel ch = vlv_dport_to_channel(dport);

	int pipe = intel_crtc->pipe;

	int data, i;

	int data, i, stagger;

	u32 val;



	mutex_lock(&dev_priv->dpio_lock);
@@ -2772,7 +2772,38 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder) 
	}



	/* Data lane stagger programming */

	/* FIXME: Fix up value only after power analysis */

	if (intel_crtc->config->port_clock > 270000)

		stagger = 0x18;

	else if (intel_crtc->config->port_clock > 135000)

		stagger = 0xd;

	else if (intel_crtc->config->port_clock > 67500)

		stagger = 0x7;

	else if (intel_crtc->config->port_clock > 33750)

		stagger = 0x4;

	else

		stagger = 0x2;



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));

	val |= DPIO_TX2_STAGGER_MASK(0x1f);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));

	val |= DPIO_TX2_STAGGER_MASK(0x1f);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);



	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),

		       DPIO_LANESTAGGER_STRAP(stagger) |

		       DPIO_LANESTAGGER_STRAP_OVRD |

		       DPIO_TX1_STAGGER_MASK(0x1f) |

		       DPIO_TX1_STAGGER_MULT(6) |

		       DPIO_TX2_STAGGER_MULT(0));



	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),

		       DPIO_LANESTAGGER_STRAP(stagger) |

		       DPIO_LANESTAGGER_STRAP_OVRD |

		       DPIO_TX1_STAGGER_MASK(0x1f) |

		       DPIO_TX1_STAGGER_MULT(7) |

		       DPIO_TX2_STAGGER_MULT(5));



	mutex_unlock(&dev_priv->dpio_lock);

drivers/gpu/drm/i915/intel_hdmi.c

+33 −2
Original line number Diff line number Diff line
@@ -1487,7 +1487,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) 
		&intel_crtc->config->base.adjusted_mode;

	enum dpio_channel ch = vlv_dport_to_channel(dport);

	int pipe = intel_crtc->pipe;

	int data, i;

	int data, i, stagger;

	u32 val;



	mutex_lock(&dev_priv->dpio_lock);
@@ -1527,7 +1527,38 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder) 
	}



	/* Data lane stagger programming */

	/* FIXME: Fix up value only after power analysis */

	if (intel_crtc->config->port_clock > 270000)

		stagger = 0x18;

	else if (intel_crtc->config->port_clock > 135000)

		stagger = 0xd;

	else if (intel_crtc->config->port_clock > 67500)

		stagger = 0x7;

	else if (intel_crtc->config->port_clock > 33750)

		stagger = 0x4;

	else

		stagger = 0x2;



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));

	val |= DPIO_TX2_STAGGER_MASK(0x1f);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);



	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));

	val |= DPIO_TX2_STAGGER_MASK(0x1f);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);



	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),

		       DPIO_LANESTAGGER_STRAP(stagger) |

		       DPIO_LANESTAGGER_STRAP_OVRD |

		       DPIO_TX1_STAGGER_MASK(0x1f) |

		       DPIO_TX1_STAGGER_MULT(6) |

		       DPIO_TX2_STAGGER_MULT(0));



	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),

		       DPIO_LANESTAGGER_STRAP(stagger) |

		       DPIO_LANESTAGGER_STRAP_OVRD |

		       DPIO_TX1_STAGGER_MASK(0x1f) |

		       DPIO_TX1_STAGGER_MULT(7) |

		       DPIO_TX2_STAGGER_MULT(5));



	/* Clear calc init */

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));