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Commit 2dd24a9c authored by Rodrigo Vivi's avatar Rodrigo Vivi
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drm/i915/gen11+: First assume next platforms will inherit stuff 



This exactly same approach was already used from gen9
to gen10 and from gen10 to gen11. Let's also use it
for gen11+.

Let's first assume that we inherit a similar platform
and than we apply the differences on top.

Different from the previous attempts this will be
done this time with coccinelle. We obviously need to
exclude some case that is really exclusive for gen11
like  PCH, Firmware, and few others. Luckly this was
easy to filter by selecting the files we are touching
with coccinelle as exposed below:

spatch -sp_file gen11\+.cocci --in-place i915_perf.c \
       intel_bios.c intel_cdclk.c intel_ddi.c \
       intel_device_info.c intel_display.c intel_dpll_mgr.c \
       intel_dsi_vbt.c intel_hdmi.c intel_mocs.c intel_color.c

@noticelake@ expression e; @@
-!IS_ICELAKE(e)
+INTEL_GEN(e) < 11
@notgen11@ expression e; @@
-!IS_GEN(e, 11)
+INTEL_GEN(e) < 11
@icelake@ expression e; @@
-IS_ICELAKE(e)
+INTEL_GEN(e) >= 11
@gen11@ expression e; @@
-IS_GEN(e, 11)
+INTEL_GEN(e) >= 11

No functional change.

v2: Remove intel_lrc.c per Tvrtko request since those were w/a
    for ICL hw issuea and media related configuration.

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190308214300.25057-1-rodrigo.vivi@intel.com
parent 2131bc0c

drivers/gpu/drm/i915/i915_perf.c

+1 −1
Original line number Diff line number Diff line
@@ -2881,7 +2881,7 @@ void i915_perf_register(struct drm_i915_private *dev_priv) 


	sysfs_attr_init(&dev_priv->perf.oa.test_config.sysfs_metric_id.attr);



	if (IS_ICELAKE(dev_priv)) {

	if (INTEL_GEN(dev_priv) >= 11) {

		i915_perf_load_test_config_icl(dev_priv);

	} else if (IS_CANNONLAKE(dev_priv)) {

		i915_perf_load_test_config_cnl(dev_priv);

drivers/gpu/drm/i915/intel_bios.c

+2 −2
Original line number Diff line number Diff line
@@ -2094,8 +2094,8 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, 
		dvo_port = child->dvo_port;



		if (dvo_port == DVO_PORT_MIPIA ||

		    (dvo_port == DVO_PORT_MIPIB && IS_ICELAKE(dev_priv)) ||

		    (dvo_port == DVO_PORT_MIPIC && !IS_ICELAKE(dev_priv))) {

		    (dvo_port == DVO_PORT_MIPIB && INTEL_GEN(dev_priv) >= 11) ||

		    (dvo_port == DVO_PORT_MIPIC && INTEL_GEN(dev_priv) < 11)) {

			if (port)

				*port = dvo_port - DVO_PORT_MIPIA;

			return true;

drivers/gpu/drm/i915/intel_cdclk.c

+3 −3
Original line number Diff line number Diff line
@@ -2560,7 +2560,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 
 */

void intel_update_max_cdclk(struct drm_i915_private *dev_priv)

{

	if (IS_ICELAKE(dev_priv)) {

	if (INTEL_GEN(dev_priv) >= 11) {

		if (dev_priv->cdclk.hw.ref == 24000)

			dev_priv->max_cdclk_freq = 648000;

		else
@@ -2744,7 +2744,7 @@ void intel_update_rawclk(struct drm_i915_private *dev_priv) 
 */

void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)

{

	if (IS_ICELAKE(dev_priv)) {

	if (INTEL_GEN(dev_priv) >= 11) {

		dev_priv->display.set_cdclk = icl_set_cdclk;

		dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;

	} else if (IS_CANNONLAKE(dev_priv)) {
@@ -2773,7 +2773,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 
			vlv_modeset_calc_cdclk;

	}



	if (IS_ICELAKE(dev_priv))

	if (INTEL_GEN(dev_priv) >= 11)

		dev_priv->display.get_cdclk = icl_get_cdclk;

	else if (IS_CANNONLAKE(dev_priv))

		dev_priv->display.get_cdclk = cnl_get_cdclk;

drivers/gpu/drm/i915/intel_color.c

+1 −1
Original line number Diff line number Diff line
@@ -841,7 +841,7 @@ void intel_color_init(struct intel_crtc *crtc) 


		dev_priv->display.color_commit = i9xx_color_commit;

	} else {

		if (IS_ICELAKE(dev_priv))

		if (INTEL_GEN(dev_priv) >= 11)

			dev_priv->display.load_luts = icl_load_luts;

		else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))

			dev_priv->display.load_luts = glk_load_luts;

drivers/gpu/drm/i915/intel_ddi.c

+9 −9
Original line number Diff line number Diff line
@@ -851,7 +851,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por 


	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;



	if (IS_ICELAKE(dev_priv)) {

	if (INTEL_GEN(dev_priv) >= 11) {

		if (intel_port_is_combophy(dev_priv, port))

			icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,

						0, &n_entries);
@@ -1678,7 +1678,7 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder, 
{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);



	if (IS_ICELAKE(dev_priv))

	if (INTEL_GEN(dev_priv) >= 11)

		icl_ddi_clock_get(encoder, pipe_config);

	else if (IS_CANNONLAKE(dev_priv))

		cnl_ddi_clock_get(encoder, pipe_config);
@@ -2225,7 +2225,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) 
	enum port port = encoder->port;

	int n_entries;



	if (IS_ICELAKE(dev_priv)) {

	if (INTEL_GEN(dev_priv) >= 11) {

		if (intel_port_is_combophy(dev_priv, port))

			icl_get_combo_buf_trans(dev_priv, port, encoder->type,

						intel_dp->link_rate, &n_entries);
@@ -2698,7 +2698,7 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp) 
	struct intel_encoder *encoder = &dport->base;

	int level = intel_ddi_dp_level(intel_dp);



	if (IS_ICELAKE(dev_priv))

	if (INTEL_GEN(dev_priv) >= 11)

		icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,

					level, encoder->type);

	else if (IS_CANNONLAKE(dev_priv))
@@ -2867,7 +2867,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, 


	mutex_lock(&dev_priv->dpll_lock);



	if (IS_ICELAKE(dev_priv)) {

	if (INTEL_GEN(dev_priv) >= 11) {

		if (!intel_port_is_combophy(dev_priv, port))

			I915_WRITE(DDI_CLK_SEL(port),

				   icl_pll_to_ddi_clk_sel(encoder, crtc_state));
@@ -2909,7 +2909,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) 
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum port port = encoder->port;



	if (IS_ICELAKE(dev_priv)) {

	if (INTEL_GEN(dev_priv) >= 11) {

		if (!intel_port_is_combophy(dev_priv, port))

			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);

	} else if (IS_CANNONLAKE(dev_priv)) {
@@ -3126,7 +3126,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, 
	icl_program_mg_dp_mode(dig_port);

	icl_disable_phy_clock_gating(dig_port);



	if (IS_ICELAKE(dev_priv))

	if (INTEL_GEN(dev_priv) >= 11)

		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,

					level, encoder->type);

	else if (IS_CANNONLAKE(dev_priv))
@@ -3175,7 +3175,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, 
	icl_program_mg_dp_mode(dig_port);

	icl_disable_phy_clock_gating(dig_port);



	if (IS_ICELAKE(dev_priv))

	if (INTEL_GEN(dev_priv) >= 11)

		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,

					level, INTEL_OUTPUT_HDMI);

	else if (IS_CANNONLAKE(dev_priv))
@@ -3711,7 +3711,7 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 
void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,

					 struct intel_crtc_state *crtc_state)

{

	if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)

	if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)

		crtc_state->min_voltage_level = 1;

	else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)

		crtc_state->min_voltage_level = 2;