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Commit 2cfae8fe authored by Karthik Anantha Ram's avatar Karthik Anantha Ram
Browse files

msm: camera: icp: Update a5 qos values post reset 



Update a5 R/W priorities post a5 reset.

CRs-Fixed: 2834780
Change-Id: I81736f780c70a648b81f4cd05db7caa0bdcc5195
Signed-off-by: default avatarKarthik Anantha Ram <kartanan@codeaurora.org>
parent 0490cb29

drivers/cam_icp/icp_hw/a5_hw/a5_core.c

+9 −0
Original line number Diff line number Diff line
@@ -421,6 +421,8 @@ static int cam_a5_power_resume(struct cam_hw_info *a5_info, bool debug_enabled) 
{

	uint32_t val = A5_CSR_FULL_CPU_EN;

	void __iomem *base;

	struct cam_hw_soc_info *soc_info = NULL;

	struct a5_soc_info *a5_soc_info;



	if (!a5_info) {

		CAM_ERR(CAM_ICP, "invalid A5 device info");
@@ -428,6 +430,8 @@ static int cam_a5_power_resume(struct cam_hw_info *a5_info, bool debug_enabled) 
	}



	base = a5_info->soc_info.reg_map[A5_SIERRA_BASE].mem_base;

	soc_info = &a5_info->soc_info;

	a5_soc_info = soc_info->soc_private;



	cam_io_w_mb(A5_CSR_A5_CPU_EN, base + ICP_SIERRA_A5_CSR_A5_CONTROL);

	cam_io_w_mb(A5_CSR_FUNC_RESET, base + ICP_SIERRA_A5_CSR_NSEC_RESET);
@@ -436,6 +440,11 @@ static int cam_a5_power_resume(struct cam_hw_info *a5_info, bool debug_enabled) 
		val |= A5_CSR_FULL_DBG_EN;



	cam_io_w_mb(val, base + ICP_SIERRA_A5_CSR_A5_CONTROL);

	cam_io_w_mb(a5_soc_info->a5_qos_val,

		base + ICP_SIERRA_A5_CSR_ACCESS);



	CAM_DBG(CAM_ICP, "a5 qos-val : 0x%x",

		cam_io_r_mb(base + ICP_SIERRA_A5_CSR_ACCESS));



	return 0;

}