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Commit 2cddf747 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 5.4-rc1-prerelease into android-mainline 



To make the 5.4-rc1 merge easier, merge at a prerelease point in time
before the final release happens.

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
Change-Id: I052c6a28528e10cdda89b6a20d320ac7562266b8
parents 00620c7e 8f744bde

Documentation/ABI/testing/sysfs-class-watchdog

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@@ -72,3 +72,37 @@ Description: 
		It is a read/write file. When read, the currently assigned

		pretimeout governor is returned.  When written, it sets

		the pretimeout governor.



What:		/sys/class/watchdog/watchdog1/access_cs0

Date:		August 2019

Contact:	Ivan Mikhaylov <i.mikhaylov@yadro.com>,

		Alexander Amelkin <a.amelkin@yadro.com>

Description:

		It is a read/write file. This attribute exists only if the

		system has booted from the alternate flash chip due to

		expiration of a watchdog timer of AST2400/AST2500 when

		alternate boot function was enabled with 'aspeed,alt-boot'

		devicetree option for that watchdog or with an appropriate

		h/w strapping (for WDT2 only).



		At alternate flash the 'access_cs0' sysfs node provides:

			ast2400: a way to get access to the primary SPI flash

				chip at CS0 after booting from the alternate

				chip at CS1.

			ast2500: a way to restore the normal address mapping

				from (CS0->CS1, CS1->CS0) to (CS0->CS0,

				CS1->CS1).



		Clearing the boot code selection and timeout counter also

		resets to the initial state the chip select line mapping. When

		the SoC is in normal mapping state (i.e. booted from CS0),

		clearing those bits does nothing for both versions of the SoC.

		For alternate boot mode (booted from CS1 due to wdt2

		expiration) the behavior differs as described above.



		This option can be used with wdt2 (watchdog1) only.



		When read, the current status of the boot code selection is

		shown. When written with any non-zero value, it clears

		the boot code selection and the timeout counter, which results

		in chipselect reset for AST2400/AST2500.

Documentation/devicetree/bindings/pwm/pwm-mediatek.txt

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@@ -6,6 +6,8 @@ Required properties: 
   - "mediatek,mt7622-pwm": found on mt7622 SoC.

   - "mediatek,mt7623-pwm": found on mt7623 SoC.

   - "mediatek,mt7628-pwm": found on mt7628 SoC.

   - "mediatek,mt7629-pwm", "mediatek,mt7622-pwm": found on mt7629 SoC.

   - "mediatek,mt8516-pwm": found on mt8516 SoC.

 - reg: physical base address and length of the controller's registers.

 - #pwm-cells: must be 2. See pwm.txt in this directory for a description of

   the cell format.

Documentation/devicetree/bindings/pwm/pwm-sprd.txt

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Spreadtrum PWM controller



Spreadtrum SoCs PWM controller provides 4 PWM channels.



Required properties:

- compatible : Should be "sprd,ums512-pwm".

- reg: Physical base address and length of the controller's registers.

- clocks: The phandle and specifier referencing the controller's clocks.

- clock-names: Should contain following entries:

  "pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3).

  "enablen": for PWM channel n enable clock (n range: 0 ~ 3).

- #pwm-cells: Should be 2. See pwm.txt in this directory for a description of

  the cells format.



Optional properties:

- assigned-clocks: Reference to the PWM clock entries.

- assigned-clock-parents: The phandle of the parent clock of PWM clock.



Example:

	pwms: pwm@32260000 {

		compatible = "sprd,ums512-pwm";

		reg = <0 0x32260000 0 0x10000>;

		clock-names = "pwm0", "enable0",

			"pwm1", "enable1",

			"pwm2", "enable2",

			"pwm3", "enable3";

		clocks = <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>,

		       <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>,

		       <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>,

		       <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>;

		assigned-clocks = <&aon_clk CLK_PWM0>,

			<&aon_clk CLK_PWM1>,

			<&aon_clk CLK_PWM2>,

			<&aon_clk CLK_PWM3>;

		assigned-clock-parents = <&ext_26m>,

			<&ext_26m>,

			<&ext_26m>,

			<&ext_26m>;

		#pwm-cells = <2>;

	};

Documentation/devicetree/bindings/thermal/qoriq-thermal.txt

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@@ -23,6 +23,7 @@ Required properties: 
Optional property:

- little-endian : If present, the TMU registers are little endian. If absent,

	the default is big endian.

- clocks : the clock for clocking the TMU silicon.



Example:

Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/watchdog/allwinner,sun4i-a10-wdt.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Allwinner A10 Watchdog Device Tree Bindings



allOf:

  - $ref: "watchdog.yaml#"



maintainers:

  - Chen-Yu Tsai <wens@csie.org>

  - Maxime Ripard <maxime.ripard@bootlin.com>



properties:

  compatible:

    oneOf:

      - const: allwinner,sun4i-a10-wdt

      - const: allwinner,sun6i-a31-wdt

      - items:

          - const: allwinner,sun50i-a64-wdt

          - const: allwinner,sun6i-a31-wdt

      - items:

          - const: allwinner,sun50i-h6-wdt

          - const: allwinner,sun6i-a31-wdt

      - items:

          - const: allwinner,suniv-f1c100s-wdt

          - const: allwinner,sun4i-a10-wdt



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  interrupts:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - interrupts



unevaluatedProperties: false



examples:

  - |

    wdt: watchdog@1c20c90 {

        compatible = "allwinner,sun4i-a10-wdt";

        reg = <0x01c20c90 0x10>;

        interrupts = <24>;

        clocks = <&osc24M>;

        timeout-sec = <10>;

    };



...