Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2cc63b39 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull ARC fixes from Vineet Gupta:
 "Fixes for ARC for 5.0, bunch of those are stable fodder anyways so
  sooner the better.

   - Fix memcpy to prevent prefetchw beyond end of buffer [Eugeniy]

   - Enable unaligned access early to prevent exceptions given newer gcc
     code gen [Eugeniy]

   - Tighten up uboot arg checking to prevent false negatives and also
     allow both jtag and bootloading to coexist w/o config option as
     needed by kernelCi folks [Eugeniy]

   - Set slab alignment to 8 for ARC to avoid the atomic64_t unalign
     [Alexey]

   - Disable regfile auto save on interrupts on HSDK platform due to a
     silicon issue [Vineet]

   - Avoid HS38x boot printing crash by not reading HS48x only reg
     [Vineet]"

* tag 'arc-5.0-final' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARCv2: don't assume core 0x54 has dual issue
  ARC: define ARCH_SLAB_MINALIGN = 8
  ARC: enable uboot support unconditionally
  ARC: U-boot: check arguments paranoidly
  ARCv2: support manual regfile save on interrupts
  ARC: uacces: remove lp_start, lp_end from clobber list
  ARC: fix actionpoints configuration detection
  ARCv2: lib: memcpy: fix doing prefetchw outside of buffer
  ARCv2: Enable unaligned access in early ASM code
parents 8456e98e 7b2e932f
Loading
Loading
Loading
Loading
+8 −12
Original line number Diff line number Diff line
@@ -191,7 +191,6 @@ config NR_CPUS

config ARC_SMP_HALT_ON_RESET
	bool "Enable Halt-on-reset boot mode"
	default y if ARC_UBOOT_SUPPORT
	help
	  In SMP configuration cores can be configured as Halt-on-reset
	  or they could all start at same time. For Halt-on-reset, non
@@ -407,6 +406,14 @@ config ARC_HAS_ACCL_REGS
	  (also referred to as r58:r59). These can also be used by gcc as GPR so
	  kernel needs to save/restore per process

config ARC_IRQ_NO_AUTOSAVE
	bool "Disable hardware autosave regfile on interrupts"
	default n
	help
	  On HS cores, taken interrupt auto saves the regfile on stack.
	  This is programmable and can be optionally disabled in which case
	  software INTERRUPT_PROLOGUE/EPILGUE do the needed work

endif	# ISA_ARCV2

endmenu   # "ARC CPU Configuration"
@@ -515,17 +522,6 @@ config ARC_DBG_TLB_PARANOIA

endif

config ARC_UBOOT_SUPPORT
	bool "Support uboot arg Handling"
	help
	  ARC Linux by default checks for uboot provided args as pointers to
	  external cmdline or DTB. This however breaks in absence of uboot,
	  when booting from Metaware debugger directly, as the registers are
	  not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
	  registers look like uboot args to kernel which then chokes.
	  So only enable the uboot arg checking/processing if users are sure
	  of uboot being in play.

config ARC_BUILTIN_DTB_NAME
	string "Built in DTB"
	help
+0 −1
Original line number Diff line number Diff line
@@ -31,7 +31,6 @@ CONFIG_ARC_CACHE_LINE_SHIFT=5
# CONFIG_ARC_HAS_LLSC is not set
CONFIG_ARC_KVADDR_SIZE=402
CONFIG_ARC_EMUL_UNALIGNED=y
CONFIG_ARC_UBOOT_SUPPORT=y
CONFIG_PREEMPT=y
CONFIG_NET=y
CONFIG_UNIX=y
+0 −1
Original line number Diff line number Diff line
@@ -13,7 +13,6 @@ CONFIG_PARTITION_ADVANCED=y
CONFIG_ARC_PLAT_AXS10X=y
CONFIG_AXS103=y
CONFIG_ISA_ARCV2=y
CONFIG_ARC_UBOOT_SUPPORT=y
CONFIG_ARC_BUILTIN_DTB_NAME="vdk_hs38"
CONFIG_PREEMPT=y
CONFIG_NET=y
+0 −2
Original line number Diff line number Diff line
@@ -15,8 +15,6 @@ CONFIG_AXS103=y
CONFIG_ISA_ARCV2=y
CONFIG_SMP=y
# CONFIG_ARC_TIMERS_64BIT is not set
# CONFIG_ARC_SMP_HALT_ON_RESET is not set
CONFIG_ARC_UBOOT_SUPPORT=y
CONFIG_ARC_BUILTIN_DTB_NAME="vdk_hs38_smp"
CONFIG_PREEMPT=y
CONFIG_NET=y
+8 −0
Original line number Diff line number Diff line
@@ -151,6 +151,14 @@ struct bcr_isa_arcv2 {
#endif
};

struct bcr_uarch_build_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:8, prod:8, maj:8, min:8;
#else
	unsigned int min:8, maj:8, prod:8, pad:8;
#endif
};

struct bcr_mpy {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
Loading