Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2c574e1a authored by Johan Jonker's avatar Johan Jonker Committed by Greg Kroah-Hartman
Browse files

arm64: dts: rockchip: add #power-domain-cells to power domain nodes 



[ Upstream commit 837188d49823230f47afdbbec7556740e89a8557 ]

Add #power-domain-cells to power domain nodes, because they
are required by power-domain.yaml

Signed-off-by: default avatarJohan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20210417112952.8516-9-jbx6244@gmail.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Stable-dep-of: 3699f2c43ea9 ("arm64: dts: rockchip: add hevc power domain clock to rk3328")
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 2aa7a508

arch/arm64/boot/dts/rockchip/px30.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -219,12 +219,14 @@ 
					 <&cru HCLK_OTG>,

					 <&cru SCLK_OTG_ADP>;

				pm_qos = <&qos_usb_host>, <&qos_usb_otg>;

				#power-domain-cells = <0>;

			};

			power-domain@PX30_PD_SDCARD {

				reg = <PX30_PD_SDCARD>;

				clocks = <&cru HCLK_SDMMC>,

					 <&cru SCLK_SDMMC>;

				pm_qos = <&qos_sdmmc>;

				#power-domain-cells = <0>;

			};

			power-domain@PX30_PD_GMAC {

				reg = <PX30_PD_GMAC>;
@@ -233,6 +235,7 @@ 
					 <&cru SCLK_MAC_REF>,

					 <&cru SCLK_GMAC_RX_TX>;

				pm_qos = <&qos_gmac>;

				#power-domain-cells = <0>;

			};

			power-domain@PX30_PD_MMC_NAND {

				reg = <PX30_PD_MMC_NAND>;
@@ -246,6 +249,7 @@ 
					  <&cru SCLK_SFC>;

				pm_qos = <&qos_emmc>, <&qos_nand>,

					 <&qos_sdio>, <&qos_sfc>;

				#power-domain-cells = <0>;

			};

			power-domain@PX30_PD_VPU {

				reg = <PX30_PD_VPU>;
@@ -253,6 +257,7 @@ 
					 <&cru HCLK_VPU>,

					 <&cru SCLK_CORE_VPU>;

				pm_qos = <&qos_vpu>, <&qos_vpu_r128>;

				#power-domain-cells = <0>;

			};

			power-domain@PX30_PD_VO {

				reg = <PX30_PD_VO>;
@@ -269,6 +274,7 @@ 
					 <&cru SCLK_VOPB_PWM>;

				pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,

					 <&qos_vop_m0>, <&qos_vop_m1>;

				#power-domain-cells = <0>;

			};

			power-domain@PX30_PD_VI {

				reg = <PX30_PD_VI>;
@@ -280,11 +286,13 @@ 
				pm_qos = <&qos_isp_128>, <&qos_isp_rd>,

					 <&qos_isp_wr>, <&qos_isp_m1>,

					 <&qos_vip>;

				#power-domain-cells = <0>;

			};

			power-domain@PX30_PD_GPU {

				reg = <PX30_PD_GPU>;

				clocks = <&cru SCLK_GPU>;

				pm_qos = <&qos_gpu>;

				#power-domain-cells = <0>;

			};

		};

	};

arch/arm64/boot/dts/rockchip/rk3328.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -272,13 +272,16 @@ 


			power-domain@RK3328_PD_HEVC {

				reg = <RK3328_PD_HEVC>;

				#power-domain-cells = <0>;

			};

			power-domain@RK3328_PD_VIDEO {

				reg = <RK3328_PD_VIDEO>;

				#power-domain-cells = <0>;

			};

			power-domain@RK3328_PD_VPU {

				reg = <RK3328_PD_VPU>;

				clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;

				#power-domain-cells = <0>;

			};

		};

arch/arm64/boot/dts/rockchip/rk3399.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -1001,6 +1001,7 @@ 
				clocks = <&cru ACLK_IEP>,

					 <&cru HCLK_IEP>;

				pm_qos = <&qos_iep>;

				#power-domain-cells = <0>;

			};

			pd_rga@RK3399_PD_RGA {

				reg = <RK3399_PD_RGA>;
@@ -1008,12 +1009,14 @@ 
					 <&cru HCLK_RGA>;

				pm_qos = <&qos_rga_r>,

					 <&qos_rga_w>;

				#power-domain-cells = <0>;

			};

			pd_vcodec@RK3399_PD_VCODEC {

				reg = <RK3399_PD_VCODEC>;

				clocks = <&cru ACLK_VCODEC>,

					 <&cru HCLK_VCODEC>;

				pm_qos = <&qos_video_m0>;

				#power-domain-cells = <0>;

			};

			pd_vdu@RK3399_PD_VDU {

				reg = <RK3399_PD_VDU>;
@@ -1021,6 +1024,7 @@ 
					 <&cru HCLK_VDU>;

				pm_qos = <&qos_video_m1_r>,

					 <&qos_video_m1_w>;

				#power-domain-cells = <0>;

			};



			/* These power domains are grouped by VD_GPU */
@@ -1028,53 +1032,63 @@ 
				reg = <RK3399_PD_GPU>;

				clocks = <&cru ACLK_GPU>;

				pm_qos = <&qos_gpu>;

				#power-domain-cells = <0>;

			};



			/* These power domains are grouped by VD_LOGIC */

			pd_edp@RK3399_PD_EDP {

				reg = <RK3399_PD_EDP>;

				clocks = <&cru PCLK_EDP_CTRL>;

				#power-domain-cells = <0>;

			};

			pd_emmc@RK3399_PD_EMMC {

				reg = <RK3399_PD_EMMC>;

				clocks = <&cru ACLK_EMMC>;

				pm_qos = <&qos_emmc>;

				#power-domain-cells = <0>;

			};

			pd_gmac@RK3399_PD_GMAC {

				reg = <RK3399_PD_GMAC>;

				clocks = <&cru ACLK_GMAC>,

					 <&cru PCLK_GMAC>;

				pm_qos = <&qos_gmac>;

				#power-domain-cells = <0>;

			};

			pd_sd@RK3399_PD_SD {

				reg = <RK3399_PD_SD>;

				clocks = <&cru HCLK_SDMMC>,

					 <&cru SCLK_SDMMC>;

				pm_qos = <&qos_sd>;

				#power-domain-cells = <0>;

			};

			pd_sdioaudio@RK3399_PD_SDIOAUDIO {

				reg = <RK3399_PD_SDIOAUDIO>;

				clocks = <&cru HCLK_SDIO>;

				pm_qos = <&qos_sdioaudio>;

				#power-domain-cells = <0>;

			};

			pd_tcpc0@RK3399_PD_TCPD0 {

				reg = <RK3399_PD_TCPD0>;

				clocks = <&cru SCLK_UPHY0_TCPDCORE>,

					 <&cru SCLK_UPHY0_TCPDPHY_REF>;

				#power-domain-cells = <0>;

			};

			pd_tcpc1@RK3399_PD_TCPD1 {

				reg = <RK3399_PD_TCPD1>;

				clocks = <&cru SCLK_UPHY1_TCPDCORE>,

					 <&cru SCLK_UPHY1_TCPDPHY_REF>;

				#power-domain-cells = <0>;

			};

			pd_usb3@RK3399_PD_USB3 {

				reg = <RK3399_PD_USB3>;

				clocks = <&cru ACLK_USB3>;

				pm_qos = <&qos_usb_otg0>,

					 <&qos_usb_otg1>;

				#power-domain-cells = <0>;

			};

			pd_vio@RK3399_PD_VIO {

				reg = <RK3399_PD_VIO>;

				#power-domain-cells = <1>;

				#address-cells = <1>;

				#size-cells = <0>;
@@ -1084,6 +1098,7 @@ 
						 <&cru HCLK_HDCP>,

						 <&cru PCLK_HDCP>;

					pm_qos = <&qos_hdcp>;

					#power-domain-cells = <0>;

				};

				pd_isp0@RK3399_PD_ISP0 {

					reg = <RK3399_PD_ISP0>;
@@ -1091,6 +1106,7 @@ 
						 <&cru HCLK_ISP0>;

					pm_qos = <&qos_isp0_m0>,

						 <&qos_isp0_m1>;

					#power-domain-cells = <0>;

				};

				pd_isp1@RK3399_PD_ISP1 {

					reg = <RK3399_PD_ISP1>;
@@ -1098,9 +1114,11 @@ 
						 <&cru HCLK_ISP1>;

					pm_qos = <&qos_isp1_m0>,

						 <&qos_isp1_m1>;

					#power-domain-cells = <0>;

				};

				pd_vo@RK3399_PD_VO {

					reg = <RK3399_PD_VO>;

					#power-domain-cells = <1>;

					#address-cells = <1>;

					#size-cells = <0>;
@@ -1110,12 +1128,14 @@ 
							 <&cru HCLK_VOP0>;

						pm_qos = <&qos_vop_big_r>,

							 <&qos_vop_big_w>;

						#power-domain-cells = <0>;

					};

					pd_vopl@RK3399_PD_VOPL {

						reg = <RK3399_PD_VOPL>;

						clocks = <&cru ACLK_VOP1>,

							 <&cru HCLK_VOP1>;

						pm_qos = <&qos_vop_little>;

						#power-domain-cells = <0>;

					};

				};

			};