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Commit 2c1f9e26 authored by David S. Miller's avatar David S. Miller
Browse files


Jeff Kirsher says:

====================
100GbE Intel Wired LAN Driver Updates 2019-09-03

This series contains updates to ice driver only.

Anirudh adds the ability for the driver to handle EMP resets correctly
by adding the logic to the existing ice_reset_subtask().

Jeb fixes up the logic to properly free up the resources for a switch
rule whether or not it was successful in the removal.

Brett fixes up the reporting of ITR values to let the user know odd ITR
values are not allowed.  Fixes the driver to only disable VLAN pruning
on VLAN deletion when the VLAN being deleted is the last VLAN on the VF
VSI.

Chinh updates the driver to determine the TSA value from the priority
value when in CEE mode.

Bruce aligns the driver with the hardware specification by ensuring that
a PF reset is done as part of the unload logic.  Also update the driver
unloading field, based on the latest hardware specification, which
allows us to remove an unnecessary endian conversion.  Moves #defines
based on their need in the code.

Jesse adds the current state of auto-negotiation in the link up message.
In addition, adds additional information to inform the user of an issue
with the topology/configuration of the link.

Usha updates the driver to allow the maximum TCs that the firmware
supports, rather than hard coding to a set value.

Dave updates the DCB initialization flow to handle the case of an actual
error during DCB init.  Updated the driver to report the current stats,
even when the netdev is down, which aligns with our other drivers.

Mitch fixes the VF reset code flows to ensure that it properly calls
ice_dis_vsi_txq() to notify the firmware that the VF is being reset.

Michal fixes the driver so the DCB is not enabled when the SW LLDP is
activated, which was causing a communication issue with other NICs.  The
problem lies in that DCB was being enabled without checking the number
of TCs.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 94810bd3 cd186e51
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+3 −2
Original line number Diff line number Diff line
@@ -35,9 +35,9 @@ struct ice_aqc_get_ver {

/* Queue Shutdown (direct 0x0003) */
struct ice_aqc_q_shutdown {
	__le32 driver_unloading;
	u8 driver_unloading;
#define ICE_AQC_DRIVER_UNLOADING	BIT(0)
	u8 reserved[12];
	u8 reserved[15];
};

/* Request resource ownership (direct 0x0008)
@@ -91,6 +91,7 @@ struct ice_aqc_list_caps_elem {
#define ICE_AQC_CAPS_SRIOV				0x0012
#define ICE_AQC_CAPS_VF					0x0013
#define ICE_AQC_CAPS_VSI				0x0017
#define ICE_AQC_CAPS_DCB				0x0018
#define ICE_AQC_CAPS_RSS				0x0040
#define ICE_AQC_CAPS_RXQS				0x0041
#define ICE_AQC_CAPS_TXQS				0x0042
+13 −1
Original line number Diff line number Diff line
@@ -1275,7 +1275,7 @@ enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);

	if (unloading)
		cmd->driver_unloading = cpu_to_le32(ICE_AQC_DRIVER_UNLOADING);
		cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;

	return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
}
@@ -1594,6 +1594,18 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
					  prefix, func_p->guar_num_vsi);
			}
			break;
		case ICE_AQC_CAPS_DCB:
			caps->dcb = (number == 1);
			caps->active_tc_bitmap = logical_id;
			caps->maxtc = phys_id;
			ice_debug(hw, ICE_DBG_INIT,
				  "%s: DCB = %d\n", prefix, caps->dcb);
			ice_debug(hw, ICE_DBG_INIT,
				  "%s: active TC bitmap = %d\n", prefix,
				  caps->active_tc_bitmap);
			ice_debug(hw, ICE_DBG_INIT,
				  "%s: TC max = %d\n", prefix, caps->maxtc);
			break;
		case ICE_AQC_CAPS_RSS:
			caps->rss_table_size = number;
			caps->rss_table_entry_width = logical_id;
+7 −1
Original line number Diff line number Diff line
@@ -444,9 +444,15 @@ ice_parse_cee_pgcfg_tlv(struct ice_cee_feat_tlv *tlv,
	 *        |pg0|pg1|pg2|pg3|pg4|pg5|pg6|pg7|
	 *        ---------------------------------
	 */
	ice_for_each_traffic_class(i)
	ice_for_each_traffic_class(i) {
		etscfg->tcbwtable[i] = buf[offset++];

		if (etscfg->prio_table[i] == ICE_CEE_PGID_STRICT)
			dcbcfg->etscfg.tsatable[i] = ICE_IEEE_TSA_STRICT;
		else
			dcbcfg->etscfg.tsatable[i] = ICE_IEEE_TSA_ETS;
	}

	/* Number of TCs supported (1 octet) */
	etscfg->maxtcs = buf[offset];
}
+10 −6
Original line number Diff line number Diff line
@@ -413,7 +413,7 @@ static int ice_dcb_sw_dflt_cfg(struct ice_pf *pf, bool locked)
	memset(&pi->local_dcbx_cfg, 0, sizeof(*dcbcfg));

	dcbcfg->etscfg.willing = 1;
	dcbcfg->etscfg.maxtcs = 8;
	dcbcfg->etscfg.maxtcs = hw->func_caps.common_cap.maxtc;
	dcbcfg->etscfg.tcbwtable[0] = 100;
	dcbcfg->etscfg.tsatable[0] = ICE_IEEE_TSA_ETS;

@@ -422,7 +422,7 @@ static int ice_dcb_sw_dflt_cfg(struct ice_pf *pf, bool locked)
	dcbcfg->etsrec.willing = 0;

	dcbcfg->pfc.willing = 1;
	dcbcfg->pfc.pfccap = IEEE_8021QAZ_MAX_TCS;
	dcbcfg->pfc.pfccap = hw->func_caps.common_cap.maxtc;

	dcbcfg->numapps = 1;
	dcbcfg->app[0].selector = ICE_APP_SEL_ETHTYPE;
@@ -452,11 +452,18 @@ int ice_init_pf_dcb(struct ice_pf *pf, bool locked)
	port_info = hw->port_info;

	err = ice_init_dcb(hw);
	if (err && !port_info->is_sw_lldp) {
		dev_err(&pf->pdev->dev, "Error initializing DCB %d\n", err);
		goto dcb_init_err;
	}

	dev_info(&pf->pdev->dev,
		 "DCB is enabled in the hardware, max number of TCs supported on this port are %d\n",
		 pf->hw.func_caps.common_cap.maxtc);
	if (err) {
		/* FW LLDP is disabled, activate SW DCBX/LLDP mode */
		dev_info(&pf->pdev->dev,
			 "FW LLDP is disabled, DCBx/LLDP in SW mode.\n");
		port_info->is_sw_lldp = true;
		clear_bit(ICE_FLAG_FW_LLDP_AGENT, pf->flags);
		err = ice_dcb_sw_dflt_cfg(pf, locked);
		if (err) {
@@ -468,11 +475,9 @@ int ice_init_pf_dcb(struct ice_pf *pf, bool locked)

		pf->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
		set_bit(ICE_FLAG_DCB_CAPABLE, pf->flags);
		set_bit(ICE_FLAG_DCB_ENA, pf->flags);
		return 0;
	}

	port_info->is_sw_lldp = false;
	set_bit(ICE_FLAG_FW_LLDP_AGENT, pf->flags);

	/* DCBX in FW and LLDP enabled in FW */
@@ -484,7 +489,6 @@ int ice_init_pf_dcb(struct ice_pf *pf, bool locked)
	if (err)
		goto dcb_init_err;

	dev_info(&pf->pdev->dev, "DCBX offload supported\n");
	return err;

dcb_init_err:
+44 −44
Original line number Diff line number Diff line
@@ -3253,25 +3253,25 @@ static int
ice_set_rc_coalesce(enum ice_container_type c_type, struct ethtool_coalesce *ec,
		    struct ice_ring_container *rc, struct ice_vsi *vsi)
{
	const char *c_type_str = (c_type == ICE_RX_CONTAINER) ? "rx" : "tx";
	u32 use_adaptive_coalesce, coalesce_usecs;
	struct ice_pf *pf = vsi->back;
	u16 itr_setting;

	if (!rc->ring)
		return -EINVAL;

	itr_setting = rc->itr_setting & ~ICE_ITR_DYNAMIC;

	switch (c_type) {
	case ICE_RX_CONTAINER:
		if (ec->rx_coalesce_usecs_high > ICE_MAX_INTRL ||
		    (ec->rx_coalesce_usecs_high &&
		     ec->rx_coalesce_usecs_high < pf->hw.intrl_gran)) {
			netdev_info(vsi->netdev,
				    "Invalid value, rx-usecs-high valid values are 0 (disabled), %d-%d\n",
				    pf->hw.intrl_gran, ICE_MAX_INTRL);
				    "Invalid value, %s-usecs-high valid values are 0 (disabled), %d-%d\n",
				    c_type_str, pf->hw.intrl_gran,
				    ICE_MAX_INTRL);
			return -EINVAL;
		}

		if (ec->rx_coalesce_usecs_high != rc->ring->q_vector->intrl) {
			rc->ring->q_vector->intrl = ec->rx_coalesce_usecs_high;
			wr32(&pf->hw, GLINT_RATE(rc->ring->q_vector->reg_idx),
@@ -3279,58 +3279,58 @@ ice_set_rc_coalesce(enum ice_container_type c_type, struct ethtool_coalesce *ec,
						   pf->hw.intrl_gran));
		}

		if (ec->rx_coalesce_usecs != itr_setting &&
		    ec->use_adaptive_rx_coalesce) {
		use_adaptive_coalesce = ec->use_adaptive_rx_coalesce;
		coalesce_usecs = ec->rx_coalesce_usecs;

		break;
	case ICE_TX_CONTAINER:
		if (ec->tx_coalesce_usecs_high) {
			netdev_info(vsi->netdev,
				    "Rx interrupt throttling cannot be changed if adaptive-rx is enabled\n");
				    "setting %s-usecs-high is not supported\n",
				    c_type_str);
			return -EINVAL;
		}

		if (ec->rx_coalesce_usecs > ICE_ITR_MAX) {
			netdev_info(vsi->netdev,
				    "Invalid value, rx-usecs range is 0-%d\n",
				   ICE_ITR_MAX);
		use_adaptive_coalesce = ec->use_adaptive_tx_coalesce;
		coalesce_usecs = ec->tx_coalesce_usecs;

		break;
	default:
		dev_dbg(&pf->pdev->dev, "Invalid container type %d\n", c_type);
		return -EINVAL;
	}

		if (ec->use_adaptive_rx_coalesce) {
			rc->itr_setting |= ICE_ITR_DYNAMIC;
		} else {
			rc->itr_setting = ITR_REG_ALIGN(ec->rx_coalesce_usecs);
			rc->target_itr = ITR_TO_REG(rc->itr_setting);
		}
		break;
	case ICE_TX_CONTAINER:
		if (ec->tx_coalesce_usecs_high) {
	itr_setting = rc->itr_setting & ~ICE_ITR_DYNAMIC;
	if (coalesce_usecs != itr_setting && use_adaptive_coalesce) {
		netdev_info(vsi->netdev,
				    "setting tx-usecs-high is not supported\n");
			    "%s interrupt throttling cannot be changed if adaptive-%s is enabled\n",
			    c_type_str, c_type_str);
		return -EINVAL;
	}

		if (ec->tx_coalesce_usecs != itr_setting &&
		    ec->use_adaptive_tx_coalesce) {
	if (coalesce_usecs > ICE_ITR_MAX) {
		netdev_info(vsi->netdev,
				    "Tx interrupt throttling cannot be changed if adaptive-tx is enabled\n");
			    "Invalid value, %s-usecs range is 0-%d\n",
			    c_type_str, ICE_ITR_MAX);
		return -EINVAL;
	}

		if (ec->tx_coalesce_usecs > ICE_ITR_MAX) {
	/* hardware only supports an ITR granularity of 2us */
	if (coalesce_usecs % 2 != 0) {
		netdev_info(vsi->netdev,
				    "Invalid value, tx-usecs range is 0-%d\n",
				   ICE_ITR_MAX);
			    "Invalid value, %s-usecs must be even\n",
			    c_type_str);
		return -EINVAL;
	}

		if (ec->use_adaptive_tx_coalesce) {
	if (use_adaptive_coalesce) {
		rc->itr_setting |= ICE_ITR_DYNAMIC;
	} else {
			rc->itr_setting = ITR_REG_ALIGN(ec->tx_coalesce_usecs);
			rc->target_itr = ITR_TO_REG(rc->itr_setting);
		}
		break;
	default:
		dev_dbg(&pf->pdev->dev, "Invalid container type %d\n", c_type);
		return -EINVAL;
		/* store user facing value how it was set */
		rc->itr_setting = coalesce_usecs;
		/* set to static and convert to value HW understands */
		rc->target_itr =
			ITR_TO_REG(ITR_REG_ALIGN(rc->itr_setting));
	}

	return 0;
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