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Commit 2bf1071a authored by Nicholas Piggin's avatar Nicholas Piggin Committed by Michael Ellerman
Browse files

powerpc/64s: Remove POWER9 DD1 support 



POWER9 DD1 was never a product. It is no longer supported by upstream
firmware, and it is not effectively supported in Linux due to lack of
testing.

Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
Reviewed-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
[mpe: Remove arch_make_huge_pte() entirely]
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent ce397d21

arch/powerpc/include/asm/book3s/64/hugetlb.h

+0 −20
Original line number Diff line number Diff line
@@ -32,26 +32,6 @@ static inline int hstate_get_psize(struct hstate *hstate) 
	}

}



#define arch_make_huge_pte arch_make_huge_pte

static inline pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma,

				       struct page *page, int writable)

{

	unsigned long page_shift;



	if (!cpu_has_feature(CPU_FTR_POWER9_DD1))

		return entry;



	page_shift = huge_page_shift(hstate_vma(vma));

	/*

	 * We don't support 1G hugetlb pages yet.

	 */

	VM_WARN_ON(page_shift == mmu_psize_defs[MMU_PAGE_1G].shift);

	if (page_shift == mmu_psize_defs[MMU_PAGE_2M].shift)

		return __pte(pte_val(entry) | R_PAGE_LARGE);

	else

		return entry;

}



#ifdef CONFIG_ARCH_HAS_GIGANTIC_PAGE

static inline bool gigantic_page_supported(void)

{

arch/powerpc/include/asm/book3s/64/pgtable.h

+2 −3
Original line number Diff line number Diff line
@@ -474,9 +474,8 @@ static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, 
{

	if (full && radix_enabled()) {

		/*

		 * Let's skip the DD1 style pte update here. We know that

		 * this is a full mm pte clear and hence can be sure there is

		 * no parallel set_pte.

		 * We know that this is a full mm pte clear and

		 * hence can be sure there is no parallel set_pte.

		 */

		return radix__ptep_get_and_clear_full(mm, addr, ptep, full);

	}

arch/powerpc/include/asm/book3s/64/radix.h

+5 −30
Original line number Diff line number Diff line
@@ -12,12 +12,6 @@ 
#include <asm/book3s/64/radix-4k.h>

#endif



/*

 * For P9 DD1 only, we need to track whether the pte's huge.

 */

#define R_PAGE_LARGE	_RPAGE_RSV1





#ifndef __ASSEMBLY__

#include <asm/book3s/64/tlbflush-radix.h>

#include <asm/cpu_has_feature.h>
@@ -154,19 +148,6 @@ static inline unsigned long radix__pte_update(struct mm_struct *mm, 
{

	unsigned long old_pte;



	if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {



		unsigned long new_pte;



		old_pte = __radix_pte_update(ptep, ~0ul, 0);

		/*

		 * new value of pte

		 */

		new_pte = (old_pte | set) & ~clr;

		radix__flush_tlb_pte_p9_dd1(old_pte, mm, addr);

		if (new_pte)

			__radix_pte_update(ptep, 0, new_pte);

	} else

	old_pte = __radix_pte_update(ptep, clr, set);

	if (!huge)

		assert_pte_locked(mm, addr);
@@ -253,8 +234,6 @@ static inline int radix__pmd_trans_huge(pmd_t pmd) 


static inline pmd_t radix__pmd_mkhuge(pmd_t pmd)

{

	if (cpu_has_feature(CPU_FTR_POWER9_DD1))

		return __pmd(pmd_val(pmd) | _PAGE_PTE | R_PAGE_LARGE);

	return __pmd(pmd_val(pmd) | _PAGE_PTE);

}
@@ -285,18 +264,14 @@ static inline unsigned long radix__get_tree_size(void) 
	unsigned long rts_field;

	/*

	 * We support 52 bits, hence:

	 *  DD1    52-28 = 24, 0b11000

	 *  Others 52-31 = 21, 0b10101

	 * bits 52 - 31 = 21, 0b10101

	 * RTS encoding details

	 * bits 0 - 3 of rts -> bits 6 - 8 unsigned long

	 * bits 4 - 5 of rts -> bits 62 - 63 of unsigned long

	 */

	if (cpu_has_feature(CPU_FTR_POWER9_DD1))

		rts_field = (0x3UL << 61);

	else {

	rts_field = (0x5UL << 5); /* 6 - 8 bits */

	rts_field |= (0x2UL << 61);

	}



	return rts_field;

}

arch/powerpc/include/asm/book3s/64/tlbflush-radix.h

+0 −2
Original line number Diff line number Diff line
@@ -48,8 +48,6 @@ extern void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmad 
extern void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr);

extern void radix__flush_tlb_collapsed_pmd(struct mm_struct *mm, unsigned long addr);

extern void radix__flush_tlb_all(void);

extern void radix__flush_tlb_pte_p9_dd1(unsigned long old_pte, struct mm_struct *mm,

					unsigned long address);



extern void radix__flush_tlb_lpid_page(unsigned int lpid,

					unsigned long addr,

arch/powerpc/include/asm/cputable.h

+4 −9
Original line number Diff line number Diff line
@@ -210,7 +210,6 @@ static inline void cpu_feature_keys_init(void) { } 
#define CPU_FTR_DAWR			LONG_ASM_CONST(0x0000008000000000)

#define CPU_FTR_DABRX			LONG_ASM_CONST(0x0000010000000000)

#define CPU_FTR_PMAO_BUG		LONG_ASM_CONST(0x0000020000000000)

#define CPU_FTR_POWER9_DD1		LONG_ASM_CONST(0x0000040000000000)

#define CPU_FTR_POWER9_DD2_1		LONG_ASM_CONST(0x0000080000000000)

#define CPU_FTR_P9_TM_HV_ASSIST		LONG_ASM_CONST(0x0000100000000000)

#define CPU_FTR_P9_TM_XER_SO_BUG	LONG_ASM_CONST(0x0000200000000000)
@@ -464,8 +463,6 @@ static inline void cpu_feature_keys_init(void) { } 
	    CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \

	    CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY | \

	    CPU_FTR_P9_TLBIE_BUG | CPU_FTR_P9_TIDR)

#define CPU_FTRS_POWER9_DD1 ((CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD1) & \

			     (~CPU_FTR_SAO))

#define CPU_FTRS_POWER9_DD2_0 CPU_FTRS_POWER9

#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1)

#define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
@@ -489,16 +486,14 @@ static inline void cpu_feature_keys_init(void) { } 
#define CPU_FTRS_POSSIBLE	\

	    (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \

	     CPU_FTRS_POWER8_DD1 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | \

	     CPU_FTRS_POWER9 | CPU_FTRS_POWER9_DD1 | CPU_FTRS_POWER9_DD2_1 | \

	     CPU_FTRS_POWER9_DD2_2)

	     CPU_FTRS_POWER9 | CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)

#else

#define CPU_FTRS_POSSIBLE	\

	    (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \

	     CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \

	     CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \

	     CPU_FTRS_PA6T | CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | \

	     CPU_FTRS_POWER9 | CPU_FTRS_POWER9_DD1 | CPU_FTRS_POWER9_DD2_1 | \

	     CPU_FTRS_POWER9_DD2_2)

	     CPU_FTRS_POWER9 | CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)

#endif /* CONFIG_CPU_LITTLE_ENDIAN */

#endif

#else
@@ -567,7 +562,7 @@ enum { 
#define CPU_FTRS_ALWAYS \

	    (CPU_FTRS_POSSIBLE & ~CPU_FTR_HVMODE & CPU_FTRS_POWER7 & \

	     CPU_FTRS_POWER8E & CPU_FTRS_POWER8 & CPU_FTRS_POWER8_DD1 & \

	     CPU_FTRS_POWER9 & CPU_FTRS_POWER9_DD1 & CPU_FTRS_POWER9_DD2_1 & \

	     CPU_FTRS_POWER9 & CPU_FTRS_POWER9_DD2_1 & \

	     CPU_FTRS_DT_CPU_BASE)

#else

#define CPU_FTRS_ALWAYS		\
@@ -575,7 +570,7 @@ enum { 
	     CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \

	     CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \

	     CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & \

	     CPU_FTRS_POWER9 & CPU_FTRS_POWER9_DD1 & CPU_FTRS_POWER9_DD2_1 & \

	     CPU_FTRS_POWER9 & CPU_FTRS_POWER9_DD2_1 & \

	     CPU_FTRS_DT_CPU_BASE)

#endif /* CONFIG_CPU_LITTLE_ENDIAN */

#endif