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Commit 2b5f7766 authored by Fernando Pacheco's avatar Fernando Pacheco
Browse files

msm: camera: ife: Re-enable auto clock gating 



Auto clock gating was disabled to aid in certain debug scenarios.
However, for normal operation the expectation is for auto clock
gating to be enabled. The writes could be removed as enabled is the
default, but no harm in being explicit.

CRs-Fixed: 2584631
Change-Id: I63336d12b94f270c4962281e14e879a6207ea386
Signed-off-by: default avatarFernando Pacheco <fpacheco@codeaurora.org>
parent ede10a20

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c

+10 −6
Original line number Diff line number Diff line
@@ -323,19 +323,23 @@ int cam_vfe_top_ver3_init_hw(void *device_priv, 


	top_priv->hw_clk_rate = 0;



	/* Disable clock gating at IFE top */

	CAM_INFO(CAM_ISP, "Disable clock gating at IFE top");

	/**

	 * Auto clock gating is enabled by default, but no harm

	 * in setting the value we expect.

	 */

	CAM_INFO(CAM_ISP, "Enabling clock gating at IFE top");



	cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,

		common_data.common_reg->core_cgc_ovd_0, 0xFFFFFFFF);

		common_data.common_reg->core_cgc_ovd_0, 0x0);



	cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,

		common_data.common_reg->core_cgc_ovd_1, 0xFF);

		common_data.common_reg->core_cgc_ovd_1, 0x0);



	cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,

		common_data.common_reg->ahb_cgc_ovd, 0x1);

		common_data.common_reg->ahb_cgc_ovd, 0x0);



	cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,

		common_data.common_reg->noc_cgc_ovd, 0x1);

		common_data.common_reg->noc_cgc_ovd, 0x0);



	return 0;

}