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Commit 2b20b038 authored by Satya Durga Srinivasu Prabhala's avatar Satya Durga Srinivasu Prabhala
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ARM: dts: msm: update DPC properties for Lahaina 

Update DPC values for Lahaina as per latest data.

Change-Id: I2b079afab7362ecc3e3734fb7fbcc764186ea9e8
parent bde73178

qcom/lahaina.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -133,7 +133,7 @@ 
			cache-size = <0x20000>;

			cpu-release-addr = <0x0 0x90000000>;

			capacity-dmips-mhz = <1946>;

			dynamic-power-coefficient = <454>;

			dynamic-power-coefficient = <515>;

			cpu-idle-states = <&GOLD_RAIL_OFF>;

			next-level-cache = <&L2_4>;

			L2_4: l2-cache {
@@ -152,7 +152,7 @@ 
			cache-size = <0x20000>;

			cpu-release-addr = <0x0 0x90000000>;

			capacity-dmips-mhz = <1946>;

			dynamic-power-coefficient = <454>;

			dynamic-power-coefficient = <515>;

			cpu-idle-states = <&GOLD_RAIL_OFF>;

			next-level-cache = <&L2_5>;

			L2_5: l2-cache {
@@ -171,7 +171,7 @@ 
			cache-size = <0x20000>;

			cpu-release-addr = <0x0 0x90000000>;

			capacity-dmips-mhz = <1946>;

			dynamic-power-coefficient = <454>;

			dynamic-power-coefficient = <515>;

			cpu-idle-states = <&GOLD_RAIL_OFF>;

			next-level-cache = <&L2_6>;

			L2_6: l2-cache {
@@ -190,7 +190,7 @@ 
			cache-size = <0x20000>;

			cpu-release-addr = <0x0 0x90000000>;

			capacity-dmips-mhz = <2048>;

			dynamic-power-coefficient = <704>;

			dynamic-power-coefficient = <845>;

			cpu-idle-states = <&GOLD_RAIL_OFF>;

			next-level-cache = <&L2_7>;

			L2_7: l2-cache {