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Commit 2aae9b7d authored by Stuart Menefy's avatar Stuart Menefy Committed by Greg Kroah-Hartman
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drm/meson: Fix OSD1 RGB to YCbCr coefficient 



[ Upstream commit 6463d3930ba5b6addcfc8f80a4543976a2fc7656 ]

VPP_WRAP_OSD1_MATRIX_COEF22.Coeff22 is documented as being bits 0-12,
not 16-28.

Without this the output tends to have a pink hue, changing it results
in better color accuracy.

The vendor kernel doesn't use this register. However the code which
sets VIU2_OSD1_MATRIX_COEF22 also uses bits 0-12. There is a slightly
different style of registers for configuring some of the other matrices,
which do use bits 16-28 for this coefficient, but those have names
ending in MATRIX_COEF22_30, and this is not one of those.

Signed-off-by: default avatarStuart Menefy <stuart.menefy@mathembedded.com>
Fixes: 72888394 ("drm/meson: Add G12A Support for VIU setup")
Reviewed-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220908155243.687143-1-stuart.menefy@mathembedded.com


Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 5dd9cb66

drivers/gpu/drm/meson/meson_viu.c

+1 −1
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ static void meson_viu_set_g12a_osd1_matrix(struct meson_drm *priv, 
		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12));

	writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff),

		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21));

	writel((m[11] & 0x1fff) << 16,

	writel((m[11] & 0x1fff),

		priv->io_base +	_REG(VPP_WRAP_OSD1_MATRIX_COEF22));



	writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),