Loading bindings/pinctrl/qcom,direwolf-pinctrl.yaml 0 → 100644 +148 −0 Original line number Diff line number Diff line %YAML 1.2 --- $id: http://devicetree.org/schemas/bindings/pinctrl/qcom,direwolf-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Technologies, Inc. DIREWOLF TLMM block description: | This binding describes the Top Level Mode Multiplexer block found in the Direwolf platform. properties: compatible: Usage: required Value type: <string> Definition: must be "qcom,direwolf-pinctrl" reg: Usage: required Value type: <prop-encoded-array> Definition: the base address and size of the TLMM register space. interrupts: Usage: required Value type: <prop-encoded-array> Definition: should specify the TLMM summary IRQ. interrupt-controller: Usage: required Value type: <none> Definition: identifies this node as an interrupt controller #interrupt-cells: Usage: required Value type: <u32> Definition: must be 2. Specifying the pin number and flags, as defined in <dt-bindings/interrupt-controller/irq.h> gpio-controller: Usage: required Value type: <none> Definition: identifies this node as a gpio controller #gpio-cells: Usage: required Value type: <u32> Definition: must be 2. Specifying the pin number and flags, as defined in <dt-bindings/gpio/gpio.h> wakeup-parent: Usage: optional Value type: <phandle> Definition: A phandle to the wakeup interrupt controller for the SoC. Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. Please refer to pinctrl-bindings.txt in this directory for details of the common pinctrl bindings used by client devices, including the meaning of the phrase "pin configuration node". The pin configuration nodes act as a container for an arbitrary number of subnodes. Each of these subnodes represents some desired configuration for a pin, a group, or a list of pins or groups. This configuration can include the mux function to select on those pin(s)/group(s), and various pin configuration parameters, such as pull-up, drive strength, etc. PIN CONFIGURATION NODES: The name of each subnode is not important; all subnodes should be enumerated and processed purely based on their content. Each subnode only affects those parameters that are explicitly listed. In other words, a subnode that lists a mux function but no pin configuration parameters implies no information about any pin configuration parameters. Similarly, a pin subnode that describes a pullup parameter implies no information about e.g. the mux function. The following generic properties as defined in pinctrl-bindings.txt are valid to specify in a pin configuration subnode: pins: Usage: required Value type: <string-array> Definition: List of gpio pins affected by the properties specified in this subnode. Valid pins: gpio0-gpio227 Supports mux, bias and drive-strength sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, sdc2_data sdc1_rclk Supports bias and drive-strength function: Usage: required Value type: <string> Definition: Specify the alternative function to be configured for the specified pins. Functions are only valid for gpio pins. bias-disable: Usage: optional Value type: <none> Definition: The specified pins should be configured as no pull. bias-pull-down: Usage: optional Value type: <none> Definition: The specified pins should be configured as pull down. bias-pull-up: Usage: optional Value type: <none> Definition: The specified pins should be configured as pull up. output-high: Usage: optional Value type: <none> Definition: The specified pins are configured in output mode, driven high. Not valid for sdc pins. output-low: Usage: optional Value type: <none> Definition: The specified pins are configured in output mode, driven low. Not valid for sdc pins. drive-strength: Usage: optional Value type: <u32> Definition: Selects the drive strength for the specified pins, in mA. Valid values: 2, 4, 6, 8, 10, 12, 14 and 16 examples: - | tlmm: pinctrl@03000000 { compatible = "qcom,direwolf-pinctrl"; reg = <0x03000000 0xdc2000>; interrupts = <0 208 0>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; }; qcom/direwolf-pinctrl.dtsi 0 → 100644 +1 −0 Original line number Diff line number Diff line &tlmm { }; qcom/direwolf.dtsi +219 −1 Original line number Diff line number Diff line Loading @@ -172,7 +172,157 @@ soc: soc { }; reserved_memory: reserved-memory { }; reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; hyp_mem: hyp_region@80000000 { no-map; reg = <0x0 0x80000000 0x0 0x600000>; }; xbl_boot: xbl_boot_region@80600000 { no-map; reg = <0x0 0x80600000 0x0 0x200000>; }; xbl_aop_mem: xbl_aop_region@80800000 { no-map; reg = <0x0 0x80800000 0x0 0x60000>; }; cmd_db: reserved-memory@80860000 { compatible = "qcom,cmd-db"; no-map; reg = <0x0 0x80860000 0x0 0x20000>; }; gpu_prr: gpu_prr_region@80880000 { no-map; reg = <0x0 0x80880000 0x0 0x10000>; }; tpm_control: tmp_control@80890000 { no-map; reg = <0x0 0x80890000 0x0 0x10000>; }; reserved_0: reserved_0_region@808F0000 { no-map; reg = <0x0 0x808F0000 0x0 0xF000>; }; secdata: secdata_region@808FF000 { no-map; reg = <0x0 0x808FF000 0x0 0x1000>; }; smem_mem: smem_mem_region@80900000 { no-map; reg = <0x0 0x80900000 0x0 0x200000>; }; cpucp_fw: cpucp_fw_region@80B00000 { no-map; reg = <0x0 0x80B00000 0x0 0x100000>; }; lpass_ml: lpass_ml_region@0x83B00000 { no-map; reg = <0x0 0x83B00000 0x0 0xF00000>; }; adsp_rpc: adsp_rpc_remote_heap@0x84A00000 { no-map; reg = <0x0 0x84A00000 0x0 0x800000>; }; pil_camera_mem: pil_camera_region@85200000 { no-map; reg = <0x0 0x85200000 0x0 0x500000>; }; pil_spss_mem: pil_spss_mem_region@85700000 { no-map; reg = <0x0 0x85700000 0x0 0x400000>; }; pil_adsp_boot_mem: pil_adsp_boot_region@85B00000 { no-map; reg = <0x0 0x85B00000 0x0 0xA00000>; }; pil_video_mem: pil_video_region@86500000 { no-map; reg = <0x0 0x86500000 0x0 0x500000>; }; pil_adsp_mem: pil_adsp_region@86A00000 { no-map; reg = <0x0 0x86A00000 0x0 0x2000000>; }; pil_slpi_mem: pil_slpi_region@88A00000 { no-map; reg = <0x0 0x88A00000 0x0 0x1500000>; }; pil_cdsp_mem: pil_cdsp_region@89F00000 { no-map; reg = <0x0 0x89F00000 0x0 0x1e00000>; }; pil_gpu_mem: pil_gpu_region@8BD00000 { no-map; reg = <0x0 0x8BD00000 0x0 0x2000>; }; pil_smss_mem: pil_smss_region@8BE00000 { no-map; reg = <0x0 0x8BE00000 0x0 0x300000>; }; pil_reserved_mem: pil_reserved_region@8C100000 { no-map; reg = <0x0 0x8C100000 0x0 0x500000>; }; pil_cdsp1_mem: pil_cdsp1_region@8C600000 { no-map; reg = <0x0 0x8C600000 0x0 0x1E00000>; }; uefi_mem: uefi_mem_region@9F000000 { no-map; reg = <0x0 0x9F000000 0x0 0x1000000>; }; hyp_tz_mem: hyp_tz_mem_region@AEB00000 { no-map; reg = <0x0 0xAEB00000 0x0 0x11500000>; }; tz_stat_mem: adsp_rpc_mem_region@C0000000 { no-map; reg = <0x0 0xC0000000 0x0 0x100000>; }; pIMEM: pIMEM_valut_mem_region@C0100000 { no-map; reg = <0x0 0xC0100000 0x0 0x5000000>; }; /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>; reusable; alignment = <0x0 0x400000>; size = <0x0 0x2000000>; linux,cma-default; }; }; chosen { }; Loading Loading @@ -263,4 +413,72 @@ status = "disabled"; }; }; qcom,msm-imem@146bf000 { compatible = "qcom,msm-imem"; reg = <0x146bf000 0x1000>; ranges = <0x0 0x146bf000 0x1000>; #address-cells = <1>; #size-cells = <1>; mem_dump_table@10 { compatible = "qcom,msm-imem-mem_dump_table"; reg = <0x10 0x8>; }; restart_reason@65c { compatible = "qcom,msm-imem-restart_reason"; reg = <0x65c 0x4>; }; dload_type@1c { compatible = "qcom,msm-imem-dload-type"; reg = <0x1c 0x4>; }; boot_stats@6b0 { compatible = "qcom,msm-imem-boot_stats"; reg = <0x6b0 0x20>; }; kaslr_offset@6d0 { compatible = "qcom,msm-imem-kaslr_offset"; reg = <0x6d0 0xc>; }; pil@94c { compatible = "qcom,msm-imem-pil"; reg = <0x94c 0xc8>; }; diag_dload@c8 { compatible = "qcom,msm-imem-diag-dload"; reg = <0xc8 0xc8>; }; }; tlmm: pinctrl@f000000 { compatible = "qcom,direwolf-pinctrl"; reg = <0x0F000000 0x1000000>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; wdog: qcom,wdt@17c10000 { compatible = "qcom,msm-watchdog"; reg = <0x17c10000 0x1000>; reg-names = "wdt-base"; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; qcom,bark-time = <11000>; qcom,pet-time = <9360>; qcom,ipi-ping; qcom,wakeup-enable; }; }; #include "direwolf-pinctrl.dtsi" Loading
bindings/pinctrl/qcom,direwolf-pinctrl.yaml 0 → 100644 +148 −0 Original line number Diff line number Diff line %YAML 1.2 --- $id: http://devicetree.org/schemas/bindings/pinctrl/qcom,direwolf-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Technologies, Inc. DIREWOLF TLMM block description: | This binding describes the Top Level Mode Multiplexer block found in the Direwolf platform. properties: compatible: Usage: required Value type: <string> Definition: must be "qcom,direwolf-pinctrl" reg: Usage: required Value type: <prop-encoded-array> Definition: the base address and size of the TLMM register space. interrupts: Usage: required Value type: <prop-encoded-array> Definition: should specify the TLMM summary IRQ. interrupt-controller: Usage: required Value type: <none> Definition: identifies this node as an interrupt controller #interrupt-cells: Usage: required Value type: <u32> Definition: must be 2. Specifying the pin number and flags, as defined in <dt-bindings/interrupt-controller/irq.h> gpio-controller: Usage: required Value type: <none> Definition: identifies this node as a gpio controller #gpio-cells: Usage: required Value type: <u32> Definition: must be 2. Specifying the pin number and flags, as defined in <dt-bindings/gpio/gpio.h> wakeup-parent: Usage: optional Value type: <phandle> Definition: A phandle to the wakeup interrupt controller for the SoC. Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. Please refer to pinctrl-bindings.txt in this directory for details of the common pinctrl bindings used by client devices, including the meaning of the phrase "pin configuration node". The pin configuration nodes act as a container for an arbitrary number of subnodes. Each of these subnodes represents some desired configuration for a pin, a group, or a list of pins or groups. This configuration can include the mux function to select on those pin(s)/group(s), and various pin configuration parameters, such as pull-up, drive strength, etc. PIN CONFIGURATION NODES: The name of each subnode is not important; all subnodes should be enumerated and processed purely based on their content. Each subnode only affects those parameters that are explicitly listed. In other words, a subnode that lists a mux function but no pin configuration parameters implies no information about any pin configuration parameters. Similarly, a pin subnode that describes a pullup parameter implies no information about e.g. the mux function. The following generic properties as defined in pinctrl-bindings.txt are valid to specify in a pin configuration subnode: pins: Usage: required Value type: <string-array> Definition: List of gpio pins affected by the properties specified in this subnode. Valid pins: gpio0-gpio227 Supports mux, bias and drive-strength sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, sdc2_data sdc1_rclk Supports bias and drive-strength function: Usage: required Value type: <string> Definition: Specify the alternative function to be configured for the specified pins. Functions are only valid for gpio pins. bias-disable: Usage: optional Value type: <none> Definition: The specified pins should be configured as no pull. bias-pull-down: Usage: optional Value type: <none> Definition: The specified pins should be configured as pull down. bias-pull-up: Usage: optional Value type: <none> Definition: The specified pins should be configured as pull up. output-high: Usage: optional Value type: <none> Definition: The specified pins are configured in output mode, driven high. Not valid for sdc pins. output-low: Usage: optional Value type: <none> Definition: The specified pins are configured in output mode, driven low. Not valid for sdc pins. drive-strength: Usage: optional Value type: <u32> Definition: Selects the drive strength for the specified pins, in mA. Valid values: 2, 4, 6, 8, 10, 12, 14 and 16 examples: - | tlmm: pinctrl@03000000 { compatible = "qcom,direwolf-pinctrl"; reg = <0x03000000 0xdc2000>; interrupts = <0 208 0>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; };
qcom/direwolf-pinctrl.dtsi 0 → 100644 +1 −0 Original line number Diff line number Diff line &tlmm { };
qcom/direwolf.dtsi +219 −1 Original line number Diff line number Diff line Loading @@ -172,7 +172,157 @@ soc: soc { }; reserved_memory: reserved-memory { }; reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; hyp_mem: hyp_region@80000000 { no-map; reg = <0x0 0x80000000 0x0 0x600000>; }; xbl_boot: xbl_boot_region@80600000 { no-map; reg = <0x0 0x80600000 0x0 0x200000>; }; xbl_aop_mem: xbl_aop_region@80800000 { no-map; reg = <0x0 0x80800000 0x0 0x60000>; }; cmd_db: reserved-memory@80860000 { compatible = "qcom,cmd-db"; no-map; reg = <0x0 0x80860000 0x0 0x20000>; }; gpu_prr: gpu_prr_region@80880000 { no-map; reg = <0x0 0x80880000 0x0 0x10000>; }; tpm_control: tmp_control@80890000 { no-map; reg = <0x0 0x80890000 0x0 0x10000>; }; reserved_0: reserved_0_region@808F0000 { no-map; reg = <0x0 0x808F0000 0x0 0xF000>; }; secdata: secdata_region@808FF000 { no-map; reg = <0x0 0x808FF000 0x0 0x1000>; }; smem_mem: smem_mem_region@80900000 { no-map; reg = <0x0 0x80900000 0x0 0x200000>; }; cpucp_fw: cpucp_fw_region@80B00000 { no-map; reg = <0x0 0x80B00000 0x0 0x100000>; }; lpass_ml: lpass_ml_region@0x83B00000 { no-map; reg = <0x0 0x83B00000 0x0 0xF00000>; }; adsp_rpc: adsp_rpc_remote_heap@0x84A00000 { no-map; reg = <0x0 0x84A00000 0x0 0x800000>; }; pil_camera_mem: pil_camera_region@85200000 { no-map; reg = <0x0 0x85200000 0x0 0x500000>; }; pil_spss_mem: pil_spss_mem_region@85700000 { no-map; reg = <0x0 0x85700000 0x0 0x400000>; }; pil_adsp_boot_mem: pil_adsp_boot_region@85B00000 { no-map; reg = <0x0 0x85B00000 0x0 0xA00000>; }; pil_video_mem: pil_video_region@86500000 { no-map; reg = <0x0 0x86500000 0x0 0x500000>; }; pil_adsp_mem: pil_adsp_region@86A00000 { no-map; reg = <0x0 0x86A00000 0x0 0x2000000>; }; pil_slpi_mem: pil_slpi_region@88A00000 { no-map; reg = <0x0 0x88A00000 0x0 0x1500000>; }; pil_cdsp_mem: pil_cdsp_region@89F00000 { no-map; reg = <0x0 0x89F00000 0x0 0x1e00000>; }; pil_gpu_mem: pil_gpu_region@8BD00000 { no-map; reg = <0x0 0x8BD00000 0x0 0x2000>; }; pil_smss_mem: pil_smss_region@8BE00000 { no-map; reg = <0x0 0x8BE00000 0x0 0x300000>; }; pil_reserved_mem: pil_reserved_region@8C100000 { no-map; reg = <0x0 0x8C100000 0x0 0x500000>; }; pil_cdsp1_mem: pil_cdsp1_region@8C600000 { no-map; reg = <0x0 0x8C600000 0x0 0x1E00000>; }; uefi_mem: uefi_mem_region@9F000000 { no-map; reg = <0x0 0x9F000000 0x0 0x1000000>; }; hyp_tz_mem: hyp_tz_mem_region@AEB00000 { no-map; reg = <0x0 0xAEB00000 0x0 0x11500000>; }; tz_stat_mem: adsp_rpc_mem_region@C0000000 { no-map; reg = <0x0 0xC0000000 0x0 0x100000>; }; pIMEM: pIMEM_valut_mem_region@C0100000 { no-map; reg = <0x0 0xC0100000 0x0 0x5000000>; }; /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>; reusable; alignment = <0x0 0x400000>; size = <0x0 0x2000000>; linux,cma-default; }; }; chosen { }; Loading Loading @@ -263,4 +413,72 @@ status = "disabled"; }; }; qcom,msm-imem@146bf000 { compatible = "qcom,msm-imem"; reg = <0x146bf000 0x1000>; ranges = <0x0 0x146bf000 0x1000>; #address-cells = <1>; #size-cells = <1>; mem_dump_table@10 { compatible = "qcom,msm-imem-mem_dump_table"; reg = <0x10 0x8>; }; restart_reason@65c { compatible = "qcom,msm-imem-restart_reason"; reg = <0x65c 0x4>; }; dload_type@1c { compatible = "qcom,msm-imem-dload-type"; reg = <0x1c 0x4>; }; boot_stats@6b0 { compatible = "qcom,msm-imem-boot_stats"; reg = <0x6b0 0x20>; }; kaslr_offset@6d0 { compatible = "qcom,msm-imem-kaslr_offset"; reg = <0x6d0 0xc>; }; pil@94c { compatible = "qcom,msm-imem-pil"; reg = <0x94c 0xc8>; }; diag_dload@c8 { compatible = "qcom,msm-imem-diag-dload"; reg = <0xc8 0xc8>; }; }; tlmm: pinctrl@f000000 { compatible = "qcom,direwolf-pinctrl"; reg = <0x0F000000 0x1000000>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; wdog: qcom,wdt@17c10000 { compatible = "qcom,msm-watchdog"; reg = <0x17c10000 0x1000>; reg-names = "wdt-base"; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; qcom,bark-time = <11000>; qcom,pet-time = <9360>; qcom,ipi-ping; qcom,wakeup-enable; }; }; #include "direwolf-pinctrl.dtsi"
