ARM: dts: msm: Add LLCC entry for Yupik

		};

	};

	cache-controller@9200000 {

		compatible = "qcom,yupik-llcc","qcom,llcc-v2";

		reg = <0x9200000 0xd0000>, <0x9600000 0x50000>;

		reg-names = "llcc_base", "llcc_broadcast_base";

		cap-based-alloc-and-pwr-collapse;

		clocks = <&aopcc QDSS_CLK>;

		clock-names = "qdss_clk";

	};

	clk_virt: interconnect {

		compatible = "qcom,yupik-clk_virt";

		#interconnect-cells = <1>;