Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2a2662bf authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'perf/core-v3' of... 

Merge branch 'perf/core-v3' of git://git.kernel.org/pub/scm/linux/kernel/git/frederic/linux-dynticks

 into perf/hw_breakpoints

Pull AMD range breakpoints support from Frederic Weisbecker:

" - Extend breakpoint tools and core to support address range through perf
    event with initial backend support for AMD extended breakpoints.

    Syntax is:

           perf record -e mem:addr/len:type

    For example set write breakpoint from 0x1000 to 0x1200 (0x1000 + 512)

           perf record -e mem:0x1000/512:w

 - Clean up a bit breakpoint code validation

 It has been acked by Jiri and Oleg. "

Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents b2776bf7 36748b95

arch/x86/include/asm/cpufeature.h

+2 −0
Original line number Diff line number Diff line
@@ -174,6 +174,7 @@ 
#define X86_FEATURE_TOPOEXT	( 6*32+22) /* topology extensions CPUID leafs */

#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */

#define X86_FEATURE_PERFCTR_NB  ( 6*32+24) /* NB performance counter extensions */

#define X86_FEATURE_BPEXT	(6*32+26) /* data breakpoint extension */

#define X86_FEATURE_PERFCTR_L2	( 6*32+28) /* L2 performance counter extensions */



/*
@@ -383,6 +384,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; 
#define cpu_has_cx16		boot_cpu_has(X86_FEATURE_CX16)

#define cpu_has_eager_fpu	boot_cpu_has(X86_FEATURE_EAGER_FPU)

#define cpu_has_topoext		boot_cpu_has(X86_FEATURE_TOPOEXT)

#define cpu_has_bpext		boot_cpu_has(X86_FEATURE_BPEXT)



#if __GNUC__ >= 4

extern void warn_pre_alternatives(void);

arch/x86/include/asm/debugreg.h

+5 −0
Original line number Diff line number Diff line
@@ -114,5 +114,10 @@ static inline void debug_stack_usage_inc(void) { } 
static inline void debug_stack_usage_dec(void) { }

#endif /* X86_64 */



#ifdef CONFIG_CPU_SUP_AMD

extern void set_dr_addr_mask(unsigned long mask, int dr);

#else

static inline void set_dr_addr_mask(unsigned long mask, int dr) { }

#endif



#endif /* _ASM_X86_DEBUGREG_H */

arch/x86/include/asm/hw_breakpoint.h

+1 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
 */

struct arch_hw_breakpoint {

	unsigned long	address;

	unsigned long	mask;

	u8		len;

	u8		type;

};

arch/x86/include/asm/perf_event.h

+3 −0
Original line number Diff line number Diff line
@@ -177,6 +177,9 @@ struct x86_pmu_capability { 
#define IBS_CAPS_BRNTRGT		(1U<<5)

#define IBS_CAPS_OPCNTEXT		(1U<<6)

#define IBS_CAPS_RIPINVALIDCHK		(1U<<7)

#define IBS_CAPS_OPBRNFUSE		(1U<<8)

#define IBS_CAPS_FETCHCTLEXTD		(1U<<9)

#define IBS_CAPS_OPDATA4		(1U<<10)



#define IBS_CAPS_DEFAULT		(IBS_CAPS_AVAIL		\

					 | IBS_CAPS_FETCHSAM	\

arch/x86/include/uapi/asm/msr-index.h

+5 −0
Original line number Diff line number Diff line
@@ -206,11 +206,16 @@ 
#define MSR_AMD64_IBSOP_REG_MASK	((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)

#define MSR_AMD64_IBSCTL		0xc001103a

#define MSR_AMD64_IBSBRTARGET		0xc001103b

#define MSR_AMD64_IBSOPDATA4		0xc001103d

#define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */



/* Fam 16h MSRs */

#define MSR_F16H_L2I_PERF_CTL		0xc0010230

#define MSR_F16H_L2I_PERF_CTR		0xc0010231

#define MSR_F16H_DR1_ADDR_MASK		0xc0011019

#define MSR_F16H_DR2_ADDR_MASK		0xc001101a

#define MSR_F16H_DR3_ADDR_MASK		0xc001101b

#define MSR_F16H_DR0_ADDR_MASK		0xc0011027



/* Fam 15h MSRs */

#define MSR_F15H_PERF_CTL		0xc0010200