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Commit 29fdb6b8 authored by Daniel Baluta's avatar Daniel Baluta Committed by Shawn Guo
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arm64: dts: imx8qxp: Add lpuart1/lpuart2/lpuart3 nodes 

lpuart nodes are part of the ADMA subsystem. See Audio DMA
memory map in iMX8 QXP RM [1]

This patch is based on the dtsi file initially submitted by
Teo Hall in i.MX NXP internal tree.

[1] https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf



Signed-off-by: default avatarTeo Hall <teo.hall@nxp.com>
Signed-off-by: default avatarDaniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 071f7855

arch/arm64/boot/dts/freescale/imx8qxp.dtsi

+33 −0
Original line number Diff line number Diff line
@@ -193,6 +193,39 @@ 
			status = "disabled";

		};



		adma_lpuart1: serial@5a070000 {

			compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";

			reg = <0x5a070000 0x1000>;

			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-parent = <&gic>;

			clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;

			clock-names = "ipg";

			power-domains = <&pd IMX_SC_R_UART_1>;

			status = "disabled";

		};



		adma_lpuart2: serial@5a080000 {

			compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";

			reg = <0x5a080000 0x1000>;

			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-parent = <&gic>;

			clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;

			clock-names = "ipg";

			power-domains = <&pd IMX_SC_R_UART_2>;

			status = "disabled";

		};



		adma_lpuart3: serial@5a090000 {

			compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";

			reg = <0x5a090000 0x1000>;

			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-parent = <&gic>;

			clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;

			clock-names = "ipg";

			power-domains = <&pd IMX_SC_R_UART_3>;

			status = "disabled";

		};



		adma_i2c0: i2c@5a800000 {

			compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";

			reg = <0x5a800000 0x4000>;