Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 29de6ce5 authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
Browse files

drm/i915: Don't program DSPCLK_GATE_D twice on IVB and VLV 



We were programming register 0x42020 twice on those platforms. Once
should be enough.

Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 4d47e4f5

drivers/gpu/drm/i915/intel_pm.c

+0 −6
Original line number Diff line number Diff line
@@ -3498,11 +3498,8 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int pipe;

	uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;

	uint32_t snpcr;



	I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);



	I915_WRITE(WM3_LP_ILK, 0);

	I915_WRITE(WM2_LP_ILK, 0);

	I915_WRITE(WM1_LP_ILK, 0);
@@ -3580,9 +3577,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev) 
{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int pipe;

	uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;



	I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);



	I915_WRITE(WM3_LP_ILK, 0);

	I915_WRITE(WM2_LP_ILK, 0);