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Commit 29511735 authored by Harshdeep Dhatt's avatar Harshdeep Dhatt
Browse files

msm: kgsl: Move secvid programming to gpudev 



Since eCP will need these register writes as well, instead
of exporting a function set_secvid, move these register writes
to respective target specific functions which are common to
both eCP enabled and disabled configurations. This also helps
get rid of the register offset definitions.

Change-Id: I2faa996901c746e7277dc2fdc272b9eb76e13e9c
Signed-off-by: default avatarHarshdeep Dhatt <hdhatt@codeaurora.org>
parent cfcdc956

drivers/gpu/msm/adreno.c

+0 −26
Original line number Diff line number Diff line
@@ -1898,28 +1898,6 @@ static bool regulators_left_on(struct kgsl_device *device) 
	return false;

}



static void _set_secvid(struct kgsl_device *device)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	static bool set;



	/* Program GPU contect protection init values */

	if (device->mmu.secured && !set) {

		adreno_writereg(adreno_dev,

				ADRENO_REG_RBBM_SECVID_TSB_CONTROL, 0x0);



		adreno_writereg64(adreno_dev,

			ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,

			ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE_HI,

			KGSL_IOMMU_SECURE_BASE(&device->mmu));

		adreno_writereg(adreno_dev,

			ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_SIZE,

			KGSL_IOMMU_SECURE_SIZE);

		if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_SECVID_SET_ONCE))

			set = true;

	}

}



int adreno_switch_to_unsecure_mode(struct adreno_device *adreno_dev,

				struct adreno_ringbuffer *rb)

{
@@ -2077,8 +2055,6 @@ static int _adreno_start(struct adreno_device *adreno_dev) 
	if (status)

		goto error_oob_clear;



	_set_secvid(device);



	if (device->pwrctrl.bus_control) {

		/* VBIF waiting for RAM */

		if (adreno_dev->starved_ram_lo == 0) {
@@ -2921,8 +2897,6 @@ int adreno_soft_reset(struct kgsl_device *device) 
	adreno_ringbuffer_set_global(adreno_dev, 0);

	kgsl_mmu_set_pt(&device->mmu, device->mmu.defaultpagetable);



	_set_secvid(device);



	/* Reinitialize the GPU */

	gpudev->start(adreno_dev);

drivers/gpu/msm/adreno.h

+0 −4
Original line number Diff line number Diff line
@@ -666,10 +666,6 @@ enum adreno_regs { 
	ADRENO_REG_RBBM_PERFCTR_RBBM_0_HI,

	ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_LO,

	ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI,

	ADRENO_REG_RBBM_SECVID_TSB_CONTROL,

	ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,

	ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE_HI,

	ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_SIZE,

	ADRENO_REG_RBBM_GPR0_CNTL,

	ADRENO_REG_RBBM_GBIF_HALT,

	ADRENO_REG_RBBM_GBIF_HALT_ACK,

drivers/gpu/msm/adreno_a5xx.c

+10 −8
Original line number Diff line number Diff line
@@ -1524,6 +1524,16 @@ static void a5xx_start(struct adreno_device *adreno_dev) 
		kgsl_regrmw(device, A5XX_HLSQ_DBG_ECO_CNTL, 0x1 << 18, 0);

	}



	if (device->mmu.secured) {

		kgsl_regwrite(device, A5XX_RBBM_SECVID_TSB_CNTL, 0x0);

		kgsl_regwrite(device, A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,

			lower_32_bits(KGSL_IOMMU_SECURE_BASE(&device->mmu)));

		kgsl_regwrite(device, A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI,

			upper_32_bits(KGSL_IOMMU_SECURE_BASE(&device->mmu)));

		kgsl_regwrite(device, A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE,

			KGSL_IOMMU_SECURE_SIZE);

	}



	a5xx_preemption_start(adreno_dev);

	a5xx_protect_init(adreno_dev);

}
@@ -2400,14 +2410,6 @@ static unsigned int a5xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
				A5XX_RBBM_PERFCTR_LOAD_VALUE_LO),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI,

				A5XX_RBBM_PERFCTR_LOAD_VALUE_HI),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_CONTROL,

				A5XX_RBBM_SECVID_TSB_CNTL),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,

				A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE_HI,

				A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_SIZE,

				A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE),

	ADRENO_REG_DEFINE(ADRENO_REG_VBIF_XIN_HALT_CTRL0,

				A5XX_VBIF_XIN_HALT_CTRL0),

	ADRENO_REG_DEFINE(ADRENO_REG_VBIF_XIN_HALT_CTRL1,

drivers/gpu/msm/adreno_a6xx.c

+21 −8
Original line number Diff line number Diff line
@@ -324,6 +324,25 @@ static void a6xx_llc_configure_gpu_scid(struct adreno_device *adreno_dev); 
static void a6xx_llc_configure_gpuhtw_scid(struct adreno_device *adreno_dev);

static void a6xx_llc_enable_overrides(struct adreno_device *adreno_dev);



static void a6xx_set_secvid(struct kgsl_device *device)

{

	static bool set;



	if (set || !device->mmu.secured)

		return;



	kgsl_regwrite(device, A6XX_RBBM_SECVID_TSB_CNTL, 0x0);

	kgsl_regwrite(device, A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,

		lower_32_bits(KGSL_IOMMU_SECURE_BASE(&device->mmu)));

	kgsl_regwrite(device, A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI,

		upper_32_bits(KGSL_IOMMU_SECURE_BASE(&device->mmu)));

	kgsl_regwrite(device, A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE,

		KGSL_IOMMU_SECURE_SIZE);



	if (ADRENO_QUIRK(ADRENO_DEVICE(device), ADRENO_QUIRK_SECVID_SET_ONCE))

		set = true;

}



/*

 * Some targets support marking certain transactions as always privileged which

 * allows us to mark more memory as privileged without having to explicitly set
@@ -576,6 +595,8 @@ static void a6xx_start(struct adreno_device *adreno_dev) 


	if (ADRENO_FEATURE(adreno_dev, ADRENO_APRIV))

		kgsl_regwrite(device, A6XX_CP_APRIV_CNTL, A6XX_APRIV_DEFAULT);



	a6xx_set_secvid(device);

}



/*
@@ -2387,14 +2408,6 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
				A6XX_GMU_CM3_CFG),

	ADRENO_REG_DEFINE(ADRENO_REG_GMU_RBBM_INT_UNMASKED_STATUS,

				A6XX_GMU_RBBM_INT_UNMASKED_STATUS),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,

				A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE_HI,

				A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_SIZE,

				A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_CONTROL,

				A6XX_RBBM_SECVID_TSB_CNTL),

};



static int cpu_gpu_lock(struct cpu_gpu_lock *lock)