Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 28e53acd authored by Colin Xu's avatar Colin Xu Committed by Greg Kroah-Hartman
Browse files

drm/i915/gvt: Fix vfio_edid issue for BXT/APL 



commit 4ceb06e7c336f4a8d3f3b6ac9a4fea2e9c97dc07 upstream

BXT/APL has different isr/irr/hpd regs compared with other GEN9. If not
setting these regs bits correctly according to the emulated monitor
(currently a DP on PORT_B), although gvt still triggers a virtual HPD
event, the guest driver won't detect a valid HPD pulse thus no full
display detection will be executed to read the updated EDID.

With this patch, the vfio_edid is enabled again on BXT/APL, which is
previously disabled.

Fixes: 642403e3599e ("drm/i915/gvt: Temporarily disable vfio_edid for BXT/APL")
Signed-off-by: default avatarColin Xu <colin.xu@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20201201060329.142375-1-colin.xu@intel.com


Reviewed-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
(cherry picked from commit 4ceb06e7c336f4a8d3f3b6ac9a4fea2e9c97dc07)
Signed-off-by: default avatarColin Xu <colin.xu@intel.com>
Cc: <stable@vger.kernel.org> # 5.4.y
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 5a7c72ff

drivers/gpu/drm/i915/gvt/display.c

+61 −22
Original line number Original line Diff line number Diff line
@@ -215,6 +215,15 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
				  DDI_BUF_CTL_ENABLE);

				  DDI_BUF_CTL_ENABLE);

			vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;

			vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;

		}

		}

		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

			~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK);

		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

			~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK);

		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

			~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK);

		/* No hpd_invert set in vgpu vbt, need to clear invert mask */

		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;

		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;





		vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));

		vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));

		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=

		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
@@ -271,6 +280,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=

			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=

				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

				 TRANS_DDI_FUNC_ENABLE);

				 TRANS_DDI_FUNC_ENABLE);

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

				PORTA_HOTPLUG_ENABLE;

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

				BXT_DE_PORT_HP_DDIA;

				BXT_DE_PORT_HP_DDIA;

		}

		}
@@ -299,6 +310,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

				 (PORT_B << TRANS_DDI_PORT_SHIFT) |

				 (PORT_B << TRANS_DDI_PORT_SHIFT) |

				 TRANS_DDI_FUNC_ENABLE);

				 TRANS_DDI_FUNC_ENABLE);

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

				PORTB_HOTPLUG_ENABLE;

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

				BXT_DE_PORT_HP_DDIB;

				BXT_DE_PORT_HP_DDIB;

		}

		}
@@ -327,6 +340,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

				 (PORT_B << TRANS_DDI_PORT_SHIFT) |

				 (PORT_B << TRANS_DDI_PORT_SHIFT) |

				 TRANS_DDI_FUNC_ENABLE);

				 TRANS_DDI_FUNC_ENABLE);

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

				PORTC_HOTPLUG_ENABLE;

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

				BXT_DE_PORT_HP_DDIC;

				BXT_DE_PORT_HP_DDIC;

		}

		}
@@ -652,38 +667,62 @@ void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) 
				PORTD_HOTPLUG_STATUS_MASK;

				PORTD_HOTPLUG_STATUS_MASK;

		intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);

		intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);

	} else if (IS_BROXTON(dev_priv)) {

	} else if (IS_BROXTON(dev_priv)) {

		if (connected) {

		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {

		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= BXT_DE_PORT_HP_DDIA;

			if (connected) {

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

					BXT_DE_PORT_HP_DDIA;

			} else {

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=

					~BXT_DE_PORT_HP_DDIA;

			}

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=

				BXT_DE_PORT_HP_DDIA;

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

				~PORTA_HOTPLUG_STATUS_MASK;

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

				PORTA_HOTPLUG_LONG_DETECT;

			intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG);

		}

		}

		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {

		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {

			if (connected) {

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

					BXT_DE_PORT_HP_DDIB;

				vgpu_vreg_t(vgpu, SFUSE_STRAP) |=

				vgpu_vreg_t(vgpu, SFUSE_STRAP) |=

					SFUSE_STRAP_DDIB_DETECTED;

					SFUSE_STRAP_DDIB_DETECTED;

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= BXT_DE_PORT_HP_DDIB;

			}

			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {

				vgpu_vreg_t(vgpu, SFUSE_STRAP) |=

					SFUSE_STRAP_DDIC_DETECTED;

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |= BXT_DE_PORT_HP_DDIC;

			}

			} else {

			} else {

			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HP_DDIA;

					~BXT_DE_PORT_HP_DDIB;

			}

			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {

				vgpu_vreg_t(vgpu, SFUSE_STRAP) &=

				vgpu_vreg_t(vgpu, SFUSE_STRAP) &=

					~SFUSE_STRAP_DDIB_DETECTED;

					~SFUSE_STRAP_DDIB_DETECTED;

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HP_DDIB;

			}

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=

				BXT_DE_PORT_HP_DDIB;

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

				~PORTB_HOTPLUG_STATUS_MASK;

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

				PORTB_HOTPLUG_LONG_DETECT;

			intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);

		}

		}

		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {

		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {

			if (connected) {

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

					BXT_DE_PORT_HP_DDIC;

				vgpu_vreg_t(vgpu, SFUSE_STRAP) |=

					SFUSE_STRAP_DDIC_DETECTED;

			} else {

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=

					~BXT_DE_PORT_HP_DDIC;

				vgpu_vreg_t(vgpu, SFUSE_STRAP) &=

				vgpu_vreg_t(vgpu, SFUSE_STRAP) &=

					~SFUSE_STRAP_DDIC_DETECTED;

					~SFUSE_STRAP_DDIC_DETECTED;

				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HP_DDIC;

			}

			}

			}

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=

				BXT_DE_PORT_HP_DDIC;

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=

				~PORTC_HOTPLUG_STATUS_MASK;

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=

			PORTB_HOTPLUG_STATUS_MASK;

				PORTC_HOTPLUG_LONG_DETECT;

		intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);

			intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG);

		}

	}

	}

}

}

drivers/gpu/drm/i915/gvt/vgpu.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -432,7 +432,7 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt, 
	if (ret)

	if (ret)

		goto out_clean_sched_policy;

		goto out_clean_sched_policy;





	if (IS_BROADWELL(gvt->dev_priv))

	if (IS_BROADWELL(gvt->dev_priv) || IS_BROXTON(gvt->dev_priv))

		ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_B);

		ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_B);

	else

	else

		ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_D);

		ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_D);