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Commit 28982542 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "dt-bindings: clock: Add support for BLAIR clock controllers"

parents 15d02498 f549366d

bindings/clock/qcom,dispcc.txt

+1 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ Required properties : 
			"qcom,sm6150-dispcc"

			"qcom,sa6155-dispcc"

			"qcom,monaco-dispcc"

			"qcom,blair-dispcc"



- reg : shall contain base register location and length.

- #clock-cells : from common clock binding, shall contain 1.

bindings/clock/qcom,gcc.txt

+1 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ Required properties : 
			"qcom,sa6155-gcc"

			"qcom,monaco-gcc"

			"qcom,direwolf-gcc"

			"qcom,blair-gcc"



- reg : shall contain base register location and length

- vdd_cx-supply: The vdd_cx logic rail supply.

bindings/clock/qcom,gpucc.txt

+1 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ Required properties : 
		"qcom,sm6150-gpucc",

		"qcom,sa6155-gpucc".

		"qcom,monaco-gpucc"

		"qcom,blair-gpucc"



- reg: shall contain base register offset and size.

- reg-names: names of registers listed in the same order as in the reg property.