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Commit 2894bfa7 authored by Prateek Sood's avatar Prateek Sood
Browse files

edac: improve gold CPU cache way parsing 



Improve gold CPU cache way parsing. Gold cores uses
bit[31:28] of ERR0MISC0.

Change-Id: I24bd9f1e78829fc37eceb1a09871dab38ec8eacb
Signed-off-by: default avatarPrateek Sood <prsood@codeaurora.org>
parent febeb7a6

drivers/edac/kryo_arm64_edac.c

+26 −6
Original line number Diff line number Diff line
@@ -217,6 +217,9 @@ static int request_erp_irq(struct platform_device *pdev, const char *propname, 
static void dump_err_reg(int errorcode, int level, u64 errxstatus, u64 errxmisc,

	struct edac_device_ctl_info *edev_ctl)

{

	u32 part_num;

	int way;



	edac_printk(KERN_CRIT, EDAC_CPU, "ERRXSTATUS_EL1: %llx\n", errxstatus);

	edac_printk(KERN_CRIT, EDAC_CPU, "ERRXMISC_EL1: %llx\n", errxmisc);

	edac_printk(KERN_CRIT, EDAC_CPU, "Cache level: L%d\n", level + 1);
@@ -247,12 +250,29 @@ static void dump_err_reg(int errorcode, int level, u64 errxstatus, u64 errxmisc, 
		break;

	}



	if (level == L3)

		edac_printk(KERN_CRIT, EDAC_CPU,

			"Way: %d\n", (int) KRYO_ERRXMISC_WAY(errxmisc));

	else

	if (level == L3) {

		way = (int) KRYO_ERRXMISC_WAY(errxmisc);

	} else {

		part_num = read_cpuid_part_number();

		switch (part_num) {

		case QCOM_CPU_PART_KRYO4XX_SILVER_V1:

		case QCOM_CPU_PART_KRYO4XX_SILVER_V2:

		case QCOM_CPU_PART_KRYO6XX_SILVER_V1:

			way = (int) KRYO_ERRXMISC_WAY(errxmisc) >> 2;

			break;

		case QCOM_CPU_PART_KRYO4XX_GOLD:

		case QCOM_CPU_PART_KRYO5XX_GOLD:

		case QCOM_CPU_PART_KRYO6XX_GOLDPLUS:

			way = (int) KRYO_ERRXMISC_WAY(errxmisc);

			break;

		default:

			edac_printk(KERN_CRIT, EDAC_CPU,

			"Way: %d\n", (int) KRYO_ERRXMISC_WAY(errxmisc) >> 2);

				"Error in matching part num:%u\n", part_num);

			return;

		}

	}



	edac_printk(KERN_CRIT, EDAC_CPU, "Way: %d\n", way);

	errors[errorcode].func(edev_ctl, smp_processor_id(),

				level, errors[errorcode].msg);

}