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Commit 28924f2d authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "clk: qcom: shima: Update frequency tables and VDD data"

parents 54bc5a86 51b504fe

drivers/clk/qcom/camcc-shima.c

+33 −12
Original line number Diff line number Diff line
@@ -42,13 +42,14 @@ enum { 
};



static struct pll_vco lucid_5lpe_vco[] = {

	{ 249600000, 1750000000, 0 },

	{ 249600000, 1800000000, 0 },

};



static struct pll_vco zonda_5lpe_vco[] = {

	{ 595200000, 3600000000, 0 },

};



/* 1200MHz Configuration */

static const struct alpha_pll_config cam_cc_pll0_config = {

	.l = 0x3E,

	.alpha = 0x8000,
@@ -84,7 +85,8 @@ static struct clk_alpha_pll cam_cc_pll0 = { 
				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1500000000,

				[VDD_NOMINAL] = 1750000000},

				[VDD_NOMINAL] = 1750000000,

				[VDD_HIGH] = 1800000000},

		},

	},

};
@@ -135,6 +137,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 
	},

};



/* 600MHz Configuration */

static const struct alpha_pll_config cam_cc_pll1_config = {

	.l = 0x1F,

	.alpha = 0x4000,
@@ -170,7 +173,8 @@ static struct clk_alpha_pll cam_cc_pll1 = { 
				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1500000000,

				[VDD_NOMINAL] = 1750000000},

				[VDD_NOMINAL] = 1750000000,

				[VDD_HIGH] = 1800000000},

		},

	},

};
@@ -198,6 +202,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 
	},

};



/* 960MHz Configuration */

static const struct alpha_pll_config cam_cc_pll2_config = {

	.l = 0x32,

	.alpha = 0x0,
@@ -301,6 +306,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_early = { 
	},

};



/* 676MHz Configuration */

static const struct alpha_pll_config cam_cc_pll3_config = {

	.l = 0x23,

	.alpha = 0x3555,
@@ -336,7 +342,8 @@ static struct clk_alpha_pll cam_cc_pll3 = { 
				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1500000000,

				[VDD_NOMINAL] = 1750000000},

				[VDD_NOMINAL] = 1750000000,

				[VDD_HIGH] = 1800000000},

		},

	},

};
@@ -364,6 +371,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 
	},

};



/* 676MHz Configuration */

static const struct alpha_pll_config cam_cc_pll4_config = {

	.l = 0x23,

	.alpha = 0x3555,
@@ -399,7 +407,8 @@ static struct clk_alpha_pll cam_cc_pll4 = { 
				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1500000000,

				[VDD_NOMINAL] = 1750000000},

				[VDD_NOMINAL] = 1750000000,

				[VDD_HIGH] = 1800000000},

		},

	},

};
@@ -427,6 +436,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 
	},

};



/* 676MHz Configuration */

static const struct alpha_pll_config cam_cc_pll5_config = {

	.l = 0x23,

	.alpha = 0x3555,
@@ -462,7 +472,8 @@ static struct clk_alpha_pll cam_cc_pll5 = { 
				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1500000000,

				[VDD_NOMINAL] = 1750000000},

				[VDD_NOMINAL] = 1750000000,

				[VDD_HIGH] = 1800000000},

		},

	},

};
@@ -490,6 +501,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { 
	},

};



/* 960MHz Configuration */

static const struct alpha_pll_config cam_cc_pll6_config = {

	.l = 0x32,

	.alpha = 0x0,
@@ -525,7 +537,8 @@ static struct clk_alpha_pll cam_cc_pll6 = { 
				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1500000000,

				[VDD_NOMINAL] = 1750000000},

				[VDD_NOMINAL] = 1750000000,

				[VDD_HIGH] = 1800000000},

		},

	},

};
@@ -767,6 +780,7 @@ static struct clk_rcg2 cam_cc_cci_1_clk_src = { 


static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(320000000, P_CAM_CC_PLL6_OUT_EVEN, 1.5, 0, 0),

	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),

	{ }

};
@@ -788,7 +802,8 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 
		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_LOWER] = 400000000},

			[VDD_LOWER] = 320000000,

			[VDD_LOW] = 400000000},

	},

};
@@ -1022,12 +1037,18 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = { 
	},

};



static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),

	{ }

};



static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {

	.cmd_rcgr = 0xa040,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = cam_cc_parent_map_0,

	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,

	.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_ife_0_csid_clk_src",
@@ -1082,7 +1103,7 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { 
	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = cam_cc_parent_map_0,

	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,

	.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_ife_1_csid_clk_src",
@@ -1137,7 +1158,7 @@ static struct clk_rcg2 cam_cc_ife_2_csid_clk_src = { 
	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = cam_cc_parent_map_0,

	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,

	.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_ife_2_csid_clk_src",
@@ -1187,7 +1208,7 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { 
	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = cam_cc_parent_map_0,

	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,

	.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_ife_lite_csid_clk_src",

drivers/clk/qcom/dispcc-shima.c

+3 −2
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ enum { 
};



static struct pll_vco lucid_5lpe_vco[] = {

	{ 249600000, 1750000000, 0 },

	{ 249600000, 1800000000, 0 },

};



/* 1380MHz Configuration */
@@ -79,7 +79,8 @@ static struct clk_alpha_pll disp_cc_pll0 = { 
				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1500000000,

				[VDD_NOMINAL] = 1750000000},

				[VDD_NOMINAL] = 1750000000,

				[VDD_HIGH] = 1800000000},

		},

	},

};

drivers/clk/qcom/gcc-shima.c

+14 −9
Original line number Diff line number Diff line
@@ -62,8 +62,9 @@ static struct clk_alpha_pll gcc_gpll0 = { 
			.rate_max = (unsigned long[VDD_NUM]) {

				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1600000000,

				[VDD_NOMINAL] = 2000000000},

				[VDD_LOW_L1] = 1500000000,

				[VDD_NOMINAL] = 1750000000,

				[VDD_HIGH] = 1800000000},

		},

	},

};
@@ -132,8 +133,9 @@ static struct clk_alpha_pll gcc_gpll10 = { 
			.rate_max = (unsigned long[VDD_NUM]) {

				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1600000000,

				[VDD_NOMINAL] = 2000000000},

				[VDD_LOW_L1] = 1500000000,

				[VDD_NOMINAL] = 1750000000,

				[VDD_HIGH] = 1800000000},

		},

	},

};
@@ -158,8 +160,9 @@ static struct clk_alpha_pll gcc_gpll4 = { 
			.rate_max = (unsigned long[VDD_NUM]) {

				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1600000000,

				[VDD_NOMINAL] = 2000000000},

				[VDD_LOW_L1] = 1500000000,

				[VDD_NOMINAL] = 1750000000,

				[VDD_HIGH] = 1800000000},

		},

	},

};
@@ -184,8 +187,9 @@ static struct clk_alpha_pll gcc_gpll9 = { 
			.rate_max = (unsigned long[VDD_NUM]) {

				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1600000000,

				[VDD_NOMINAL] = 2000000000},

				[VDD_LOW_L1] = 1500000000,

				[VDD_NOMINAL] = 1750000000,

				[VDD_HIGH] = 1800000000},

		},

	},

};
@@ -1229,7 +1233,8 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 
		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_LOWER] = 100000000},

			[VDD_LOWER] = 50000000,

			[VDD_LOW_L1] = 100000000},

	},

};

drivers/clk/qcom/gpucc-shima.c

+5 −3
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ enum { 
};



static struct pll_vco lucid_5lpe_vco[] = {

	{ 249600000, 1750000000, 0 },

	{ 249600000, 1800000000, 0 },

};



/* 468MHz Configuration */
@@ -74,7 +74,8 @@ static struct clk_alpha_pll gpu_cc_pll0 = { 
				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1500000000,

				[VDD_NOMINAL] = 1750000000},

				[VDD_NOMINAL] = 1750000000,

				[VDD_HIGH] = 1800000000},

		},

	},

};
@@ -115,7 +116,8 @@ static struct clk_alpha_pll gpu_cc_pll1 = { 
				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1500000000,

				[VDD_NOMINAL] = 1750000000},

				[VDD_NOMINAL] = 1750000000,

				[VDD_HIGH] = 1800000000},

		},

	},

};

drivers/clk/qcom/videocc-shima.c

+10 −6
Original line number Diff line number Diff line
@@ -34,11 +34,12 @@ enum { 
};



static struct pll_vco lucid_5lpe_vco[] = {

	{ 249600000, 1750000000, 0 },

	{ 249600000, 1800000000, 0 },

};



/* 604.8MHz Configuration */

static const struct alpha_pll_config video_pll0_config = {

	.l = 0x25,

	.l = 0x1F,

	.alpha = 0x8000,

	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002261,
@@ -72,11 +73,13 @@ static struct clk_alpha_pll video_pll0 = { 
				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1500000000,

				[VDD_NOMINAL] = 1750000000},

				[VDD_NOMINAL] = 1750000000,

				[VDD_HIGH] = 1800000000},

		},

	},

};



/* 840MHz Configuration */

static const struct alpha_pll_config video_pll1_config = {

	.l = 0x2B,

	.alpha = 0xC000,
@@ -112,7 +115,8 @@ static struct clk_alpha_pll video_pll1 = { 
				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1500000000,

				[VDD_NOMINAL] = 1750000000},

				[VDD_NOMINAL] = 1750000000,

				[VDD_HIGH] = 1800000000},

		},

	},

};
@@ -348,7 +352,7 @@ static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = { 


static struct clk_branch video_cc_ahb_clk = {

	.halt_reg = 0xe58,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0xe58,

	.hwcg_bit = 1,

	.clkr = {
@@ -446,7 +450,7 @@ static struct clk_branch video_cc_mvs1_div2_clk = { 


static struct clk_branch video_cc_mvs1c_clk = {

	.halt_reg = 0xcd4,

	.halt_check = BRANCH_HALT_VOTED,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0xcd4,

		.enable_mask = BIT(0),