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Commit 288e4521 authored by Peter Zijlstra's avatar Peter Zijlstra Committed by Ingo Molnar
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x86/asm: 'Simplify' GEN_*_RMWcc() macros 



Currently the GEN_*_RMWcc() macros include a return statement, which
pretty much mandates we directly wrap them in a (inline) function.

Macros with return statements are tricky and, as per the above, limit
use, so remove the return statement and make them
statement-expressions. This allows them to be used more widely.

Also, shuffle the arguments a bit. Place the @cc argument as 3rd, this
makes it consistent between UNARY and BINARY, but more importantly, it
makes the @arg0 argument last.

Since the @arg0 argument is now last, we can do CPP trickery and make
it an optional argument, simplifying the users; 17 out of 18
occurences do not need this argument.

Finally, change to asm symbolic names, instead of the numeric ordering
of operands, which allows us to get rid of __BINARY_RMWcc_ARG and get
cleaner code overall.

Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: JBeulich@suse.com
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: bp@alien8.de
Cc: hpa@linux.intel.com
Link: https://lkml.kernel.org/r/20181003130957.108960094@infradead.org


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 756b1df4

arch/x86/include/asm/atomic.h

+4 −4
Original line number Diff line number Diff line
@@ -82,7 +82,7 @@ static __always_inline void arch_atomic_sub(int i, atomic_t *v) 
 */

static __always_inline bool arch_atomic_sub_and_test(int i, atomic_t *v)

{

	GEN_BINARY_RMWcc(LOCK_PREFIX "subl", v->counter, "er", i, "%0", e);

	return GEN_BINARY_RMWcc(LOCK_PREFIX "subl", v->counter, e, "er", i);

}

#define arch_atomic_sub_and_test arch_atomic_sub_and_test
@@ -122,7 +122,7 @@ static __always_inline void arch_atomic_dec(atomic_t *v) 
 */

static __always_inline bool arch_atomic_dec_and_test(atomic_t *v)

{

	GEN_UNARY_RMWcc(LOCK_PREFIX "decl", v->counter, "%0", e);

	return GEN_UNARY_RMWcc(LOCK_PREFIX "decl", v->counter, e);

}

#define arch_atomic_dec_and_test arch_atomic_dec_and_test
@@ -136,7 +136,7 @@ static __always_inline bool arch_atomic_dec_and_test(atomic_t *v) 
 */

static __always_inline bool arch_atomic_inc_and_test(atomic_t *v)

{

	GEN_UNARY_RMWcc(LOCK_PREFIX "incl", v->counter, "%0", e);

	return GEN_UNARY_RMWcc(LOCK_PREFIX "incl", v->counter, e);

}

#define arch_atomic_inc_and_test arch_atomic_inc_and_test
@@ -151,7 +151,7 @@ static __always_inline bool arch_atomic_inc_and_test(atomic_t *v) 
 */

static __always_inline bool arch_atomic_add_negative(int i, atomic_t *v)

{

	GEN_BINARY_RMWcc(LOCK_PREFIX "addl", v->counter, "er", i, "%0", s);

	return GEN_BINARY_RMWcc(LOCK_PREFIX "addl", v->counter, s, "er", i);

}

#define arch_atomic_add_negative arch_atomic_add_negative

arch/x86/include/asm/atomic64_64.h

+4 −4
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@ static inline void arch_atomic64_sub(long i, atomic64_t *v) 
 */

static inline bool arch_atomic64_sub_and_test(long i, atomic64_t *v)

{

	GEN_BINARY_RMWcc(LOCK_PREFIX "subq", v->counter, "er", i, "%0", e);

	return GEN_BINARY_RMWcc(LOCK_PREFIX "subq", v->counter, e, "er", i);

}

#define arch_atomic64_sub_and_test arch_atomic64_sub_and_test
@@ -115,7 +115,7 @@ static __always_inline void arch_atomic64_dec(atomic64_t *v) 
 */

static inline bool arch_atomic64_dec_and_test(atomic64_t *v)

{

	GEN_UNARY_RMWcc(LOCK_PREFIX "decq", v->counter, "%0", e);

	return GEN_UNARY_RMWcc(LOCK_PREFIX "decq", v->counter, e);

}

#define arch_atomic64_dec_and_test arch_atomic64_dec_and_test
@@ -129,7 +129,7 @@ static inline bool arch_atomic64_dec_and_test(atomic64_t *v) 
 */

static inline bool arch_atomic64_inc_and_test(atomic64_t *v)

{

	GEN_UNARY_RMWcc(LOCK_PREFIX "incq", v->counter, "%0", e);

	return GEN_UNARY_RMWcc(LOCK_PREFIX "incq", v->counter, e);

}

#define arch_atomic64_inc_and_test arch_atomic64_inc_and_test
@@ -144,7 +144,7 @@ static inline bool arch_atomic64_inc_and_test(atomic64_t *v) 
 */

static inline bool arch_atomic64_add_negative(long i, atomic64_t *v)

{

	GEN_BINARY_RMWcc(LOCK_PREFIX "addq", v->counter, "er", i, "%0", s);

	return GEN_BINARY_RMWcc(LOCK_PREFIX "addq", v->counter, s, "er", i);

}

#define arch_atomic64_add_negative arch_atomic64_add_negative

arch/x86/include/asm/bitops.h

+3 −6
Original line number Diff line number Diff line
@@ -217,8 +217,7 @@ static __always_inline void change_bit(long nr, volatile unsigned long *addr) 
 */

static __always_inline bool test_and_set_bit(long nr, volatile unsigned long *addr)

{

	GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(bts),

	                 *addr, "Ir", nr, "%0", c);

	return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(bts), *addr, c, "Ir", nr);

}



/**
@@ -264,8 +263,7 @@ static __always_inline bool __test_and_set_bit(long nr, volatile unsigned long * 
 */

static __always_inline bool test_and_clear_bit(long nr, volatile unsigned long *addr)

{

	GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btr),

	                 *addr, "Ir", nr, "%0", c);

	return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btr), *addr, c, "Ir", nr);

}



/**
@@ -318,8 +316,7 @@ static __always_inline bool __test_and_change_bit(long nr, volatile unsigned lon 
 */

static __always_inline bool test_and_change_bit(long nr, volatile unsigned long *addr)

{

	GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btc),

	                 *addr, "Ir", nr, "%0", c);

	return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btc), *addr, c, "Ir", nr);

}



static __always_inline bool constant_test_bit(long nr, const volatile unsigned long *addr)

arch/x86/include/asm/local.h

+4 −4
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ static inline void local_sub(long i, local_t *l) 
 */

static inline bool local_sub_and_test(long i, local_t *l)

{

	GEN_BINARY_RMWcc(_ASM_SUB, l->a.counter, "er", i, "%0", e);

	return GEN_BINARY_RMWcc(_ASM_SUB, l->a.counter, e, "er", i);

}



/**
@@ -66,7 +66,7 @@ static inline bool local_sub_and_test(long i, local_t *l) 
 */

static inline bool local_dec_and_test(local_t *l)

{

	GEN_UNARY_RMWcc(_ASM_DEC, l->a.counter, "%0", e);

	return GEN_UNARY_RMWcc(_ASM_DEC, l->a.counter, e);

}



/**
@@ -79,7 +79,7 @@ static inline bool local_dec_and_test(local_t *l) 
 */

static inline bool local_inc_and_test(local_t *l)

{

	GEN_UNARY_RMWcc(_ASM_INC, l->a.counter, "%0", e);

	return GEN_UNARY_RMWcc(_ASM_INC, l->a.counter, e);

}



/**
@@ -93,7 +93,7 @@ static inline bool local_inc_and_test(local_t *l) 
 */

static inline bool local_add_negative(long i, local_t *l)

{

	GEN_BINARY_RMWcc(_ASM_ADD, l->a.counter, "er", i, "%0", s);

	return GEN_BINARY_RMWcc(_ASM_ADD, l->a.counter, s, "er", i);

}



/**

arch/x86/include/asm/preempt.h

+1 −1
Original line number Diff line number Diff line
@@ -88,7 +88,7 @@ static __always_inline void __preempt_count_sub(int val) 
 */

static __always_inline bool __preempt_count_dec_and_test(void)

{

	GEN_UNARY_RMWcc("decl", __preempt_count, __percpu_arg(0), e);

	return GEN_UNARY_RMWcc("decl", __preempt_count, e, __percpu_arg([var]));

}



/*