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Commit 287d08a2 authored by Kalle Valo's avatar Kalle Valo
Browse files

Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git 

ath.git patches for 5.1. Major changes:

ath10k

* change QMI interface to support the new (and backwards incompatible)
  interface from HL3.1 and used in recent HL2.0 branch firmware releases

ath

* add new country codes for US
parents 3479f74e 62a2c135

drivers/net/wireless/ath/ath10k/ce.c

+62 −13
Original line number Diff line number Diff line
@@ -228,11 +228,31 @@ ath10k_ce_shadow_dest_ring_write_index_set(struct ath10k *ar, 
}



static inline void ath10k_ce_src_ring_base_addr_set(struct ath10k *ar,

						    u32 ce_id,

						    u64 addr)

{

	struct ath10k_ce *ce = ath10k_ce_priv(ar);

	struct ath10k_ce_pipe *ce_state = &ce->ce_states[ce_id];

	u32 ce_ctrl_addr = ath10k_ce_base_address(ar, ce_id);

	u32 addr_lo = lower_32_bits(addr);



	ath10k_ce_write32(ar, ce_ctrl_addr +

			  ar->hw_ce_regs->sr_base_addr_lo, addr_lo);



	if (ce_state->ops->ce_set_src_ring_base_addr_hi) {

		ce_state->ops->ce_set_src_ring_base_addr_hi(ar, ce_ctrl_addr,

							    addr);

	}

}



static void ath10k_ce_set_src_ring_base_addr_hi(struct ath10k *ar,

						u32 ce_ctrl_addr,

						    unsigned int addr)

						u64 addr)

{

	u32 addr_hi = upper_32_bits(addr) & CE_DESC_ADDR_HI_MASK;



	ath10k_ce_write32(ar, ce_ctrl_addr +

			  ar->hw_ce_regs->sr_base_addr, addr);

			  ar->hw_ce_regs->sr_base_addr_hi, addr_hi);

}



static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar,
@@ -313,11 +333,36 @@ static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar, 
}



static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar,

						     u32 ce_id,

						     u64 addr)

{

	struct ath10k_ce *ce = ath10k_ce_priv(ar);

	struct ath10k_ce_pipe *ce_state = &ce->ce_states[ce_id];

	u32 ce_ctrl_addr = ath10k_ce_base_address(ar, ce_id);

	u32 addr_lo = lower_32_bits(addr);



	ath10k_ce_write32(ar, ce_ctrl_addr +

			  ar->hw_ce_regs->dr_base_addr_lo, addr_lo);



	if (ce_state->ops->ce_set_dest_ring_base_addr_hi) {

		ce_state->ops->ce_set_dest_ring_base_addr_hi(ar, ce_ctrl_addr,

							     addr);

	}

}



static void ath10k_ce_set_dest_ring_base_addr_hi(struct ath10k *ar,

						 u32 ce_ctrl_addr,

						     u32 addr)

						 u64 addr)

{

	u32 addr_hi = upper_32_bits(addr) & CE_DESC_ADDR_HI_MASK;

	u32 reg_value;



	reg_value = ath10k_ce_read32(ar, ce_ctrl_addr +

				     ar->hw_ce_regs->dr_base_addr_hi);

	reg_value &= ~CE_DESC_ADDR_HI_MASK;

	reg_value |= addr_hi;

	ath10k_ce_write32(ar, ce_ctrl_addr +

			  ar->hw_ce_regs->dr_base_addr, addr);

			  ar->hw_ce_regs->dr_base_addr_hi, reg_value);

}



static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar,
@@ -563,7 +608,7 @@ static int _ath10k_ce_send_nolock_64(struct ath10k_ce_pipe *ce_state, 


	addr = (__le32 *)&sdesc.addr;



	flags |= upper_32_bits(buffer) & CE_DESC_FLAGS_GET_MASK;

	flags |= upper_32_bits(buffer) & CE_DESC_ADDR_HI_MASK;

	addr[0] = __cpu_to_le32(buffer);

	addr[1] = __cpu_to_le32(flags);

	if (flags & CE_SEND_FLAG_GATHER)
@@ -731,7 +776,7 @@ static int __ath10k_ce_rx_post_buf_64(struct ath10k_ce_pipe *pipe, 
		return -ENOSPC;



	desc->addr = __cpu_to_le64(paddr);

	desc->addr &= __cpu_to_le64(CE_DESC_37BIT_ADDR_MASK);

	desc->addr &= __cpu_to_le64(CE_DESC_ADDR_MASK);



	desc->nbytes = 0;
@@ -1346,7 +1391,7 @@ static int ath10k_ce_init_src_ring(struct ath10k *ar, 
		ath10k_ce_src_ring_write_index_get(ar, ctrl_addr);

	src_ring->write_index &= src_ring->nentries_mask;



	ath10k_ce_src_ring_base_addr_set(ar, ctrl_addr,

	ath10k_ce_src_ring_base_addr_set(ar, ce_id,

					 src_ring->base_addr_ce_space);

	ath10k_ce_src_ring_size_set(ar, ctrl_addr, nentries);

	ath10k_ce_src_ring_dmax_set(ar, ctrl_addr, attr->src_sz_max);
@@ -1385,7 +1430,7 @@ static int ath10k_ce_init_dest_ring(struct ath10k *ar, 
		ath10k_ce_dest_ring_write_index_get(ar, ctrl_addr);

	dest_ring->write_index &= dest_ring->nentries_mask;



	ath10k_ce_dest_ring_base_addr_set(ar, ctrl_addr,

	ath10k_ce_dest_ring_base_addr_set(ar, ce_id,

					  dest_ring->base_addr_ce_space);

	ath10k_ce_dest_ring_size_set(ar, ctrl_addr, nentries);

	ath10k_ce_dest_ring_byte_swap_set(ar, ctrl_addr, 0);
@@ -1660,7 +1705,7 @@ static void ath10k_ce_deinit_src_ring(struct ath10k *ar, unsigned int ce_id) 
{

	u32 ctrl_addr = ath10k_ce_base_address(ar, ce_id);



	ath10k_ce_src_ring_base_addr_set(ar, ctrl_addr, 0);

	ath10k_ce_src_ring_base_addr_set(ar, ce_id, 0);

	ath10k_ce_src_ring_size_set(ar, ctrl_addr, 0);

	ath10k_ce_src_ring_dmax_set(ar, ctrl_addr, 0);

	ath10k_ce_src_ring_highmark_set(ar, ctrl_addr, 0);
@@ -1670,7 +1715,7 @@ static void ath10k_ce_deinit_dest_ring(struct ath10k *ar, unsigned int ce_id) 
{

	u32 ctrl_addr = ath10k_ce_base_address(ar, ce_id);



	ath10k_ce_dest_ring_base_addr_set(ar, ctrl_addr, 0);

	ath10k_ce_dest_ring_base_addr_set(ar, ce_id, 0);

	ath10k_ce_dest_ring_size_set(ar, ctrl_addr, 0);

	ath10k_ce_dest_ring_highmark_set(ar, ctrl_addr, 0);

}
@@ -1802,6 +1847,8 @@ static const struct ath10k_ce_ops ce_ops = { 
	.ce_extract_desc_data = ath10k_ce_extract_desc_data,

	.ce_free_pipe = _ath10k_ce_free_pipe,

	.ce_send_nolock = _ath10k_ce_send_nolock,

	.ce_set_src_ring_base_addr_hi = NULL,

	.ce_set_dest_ring_base_addr_hi = NULL,

};



static const struct ath10k_ce_ops ce_64_ops = {
@@ -1814,6 +1861,8 @@ static const struct ath10k_ce_ops ce_64_ops = { 
	.ce_extract_desc_data = ath10k_ce_extract_desc_data_64,

	.ce_free_pipe = _ath10k_ce_free_pipe_64,

	.ce_send_nolock = _ath10k_ce_send_nolock_64,

	.ce_set_src_ring_base_addr_hi = ath10k_ce_set_src_ring_base_addr_hi,

	.ce_set_dest_ring_base_addr_hi = ath10k_ce_set_dest_ring_base_addr_hi,

};



static void ath10k_ce_set_ops(struct ath10k *ar,
@@ -1909,7 +1958,7 @@ void ath10k_ce_alloc_rri(struct ath10k *ar) 
			  lower_32_bits(ce->paddr_rri));

	ath10k_ce_write32(ar, ar->hw_ce_regs->ce_rri_high,

			  (upper_32_bits(ce->paddr_rri) &

			  CE_DESC_FLAGS_GET_MASK));

			  CE_DESC_ADDR_HI_MASK));



	for (i = 0; i < CE_COUNT; i++) {

		ctrl1_regs = ar->hw_ce_regs->ctrl1_regs->addr;

drivers/net/wireless/ath/ath10k/ce.h

+10 −4
Original line number Diff line number Diff line
@@ -39,8 +39,8 @@ struct ath10k_ce_pipe; 
#define CE_DESC_FLAGS_BYTE_SWAP      (1 << 1)

#define CE_WCN3990_DESC_FLAGS_GATHER BIT(31)



#define CE_DESC_FLAGS_GET_MASK		GENMASK(4, 0)

#define CE_DESC_37BIT_ADDR_MASK		GENMASK_ULL(37, 0)

#define CE_DESC_ADDR_MASK		GENMASK_ULL(34, 0)

#define CE_DESC_ADDR_HI_MASK		GENMASK(4, 0)



/* Following desc flags are used in QCA99X0 */

#define CE_DESC_FLAGS_HOST_INT_DIS	(1 << 2)
@@ -104,7 +104,7 @@ struct ath10k_ce_ring { 
	/* Host address space */

	void *base_addr_owner_space_unaligned;

	/* CE address space */

	u32 base_addr_ce_space_unaligned;

	dma_addr_t base_addr_ce_space_unaligned;



	/*

	 * Actual start of descriptors.
@@ -115,7 +115,7 @@ struct ath10k_ce_ring { 
	void *base_addr_owner_space;



	/* CE address space */

	u32 base_addr_ce_space;

	dma_addr_t base_addr_ce_space;



	char *shadow_base_unaligned;

	struct ce_desc *shadow_base;
@@ -334,6 +334,12 @@ struct ath10k_ce_ops { 
			      void *per_transfer_context,

			      dma_addr_t buffer, u32 nbytes,

			      u32 transfer_id, u32 flags);

	void (*ce_set_src_ring_base_addr_hi)(struct ath10k *ar,

					     u32 ce_ctrl_addr,

					     u64 addr);

	void (*ce_set_dest_ring_base_addr_hi)(struct ath10k *ar,

					      u32 ce_ctrl_addr,

					      u64 addr);

};



static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)

drivers/net/wireless/ath/ath10k/core.c

+11 −1
Original line number Diff line number Diff line
@@ -2309,6 +2309,10 @@ static int ath10k_core_init_firmware_features(struct ath10k *ar) 
		ar->max_num_stations = TARGET_TLV_NUM_STATIONS;

		ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS;

		ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS;

		if (ar->hif.bus == ATH10K_BUS_SDIO)

			ar->htt.max_num_pending_tx =

				TARGET_TLV_NUM_MSDU_DESC_HL;

		else

			ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC;

		ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS;

		ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
@@ -2556,6 +2560,12 @@ int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode, 
		goto err_hif_stop;

	}



	status = ath10k_hif_swap_mailbox(ar);

	if (status) {

		ath10k_err(ar, "failed to swap mailbox: %d\n", status);

		goto err_hif_stop;

	}



	if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {

		status = ath10k_htt_connect(&ar->htt);

		if (status) {

drivers/net/wireless/ath/ath10k/hif.h

+9 −0
Original line number Diff line number Diff line
@@ -59,6 +59,8 @@ struct ath10k_hif_ops { 
	 */

	void (*stop)(struct ath10k *ar);



	int (*swap_mailbox)(struct ath10k *ar);



	int (*map_service_to_pipe)(struct ath10k *ar, u16 service_id,

				   u8 *ul_pipe, u8 *dl_pipe);
@@ -139,6 +141,13 @@ static inline void ath10k_hif_stop(struct ath10k *ar) 
	return ar->hif.ops->stop(ar);

}



static inline int ath10k_hif_swap_mailbox(struct ath10k *ar)

{

	if (ar->hif.ops->swap_mailbox)

		return ar->hif.ops->swap_mailbox(ar);

	return 0;

}



static inline int ath10k_hif_map_service_to_pipe(struct ath10k *ar,

						 u16 service_id,

						 u8 *ul_pipe, u8 *dl_pipe)

drivers/net/wireless/ath/ath10k/htt.c

+1 −1
Original line number Diff line number Diff line
@@ -268,7 +268,7 @@ int ath10k_htt_setup(struct ath10k_htt *htt) 
		return status;

	}



	status = ath10k_htt_h2t_aggr_cfg_msg(htt,

	status = htt->tx_ops->htt_h2t_aggr_cfg_msg(htt,

					     htt->max_num_ampdu,

					     htt->max_num_amsdu);

	if (status) {