Merge tag 'drm-intel-next-2013-06-18' of...

	} \

} while (0)

struct file_stats {

	int count;

	size_t total, active, inactive, unbound;

};

static int per_file_stats(int id, void *ptr, void *data)

{

	struct drm_i915_gem_object *obj = ptr;

	struct file_stats *stats = data;

	stats->count++;

	stats->total += obj->base.size;

	if (obj->gtt_space) {

		if (!list_empty(&obj->ring_list))

			stats->active += obj->base.size;

		else

			stats->inactive += obj->base.size;

	} else {

		if (!list_empty(&obj->global_list))

			stats->unbound += obj->base.size;

	}

	return 0;

}

static int i915_gem_object_info(struct seq_file *m, void* data)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	u32 count, mappable_count, purgeable_count;

	size_t size, mappable_size, purgeable_size;

	struct drm_i915_gem_object *obj;

	struct drm_file *file;

	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);

		   dev_priv->mm.object_memory);

	size = count = mappable_size = mappable_count = 0;

	count_objects(&dev_priv->mm.bound_list, gtt_list);

	count_objects(&dev_priv->mm.bound_list, global_list);

	seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",

		   count, mappable_count, size, mappable_size);

		   count, mappable_count, size, mappable_size);

	size = count = purgeable_size = purgeable_count = 0;

	list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) {

	list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {

		size += obj->base.size, ++count;

		if (obj->madv == I915_MADV_DONTNEED)

			purgeable_size += obj->base.size, ++purgeable_count;

	seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);

	size = count = mappable_size = mappable_count = 0;

	list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {

	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {

		if (obj->fault_mappable) {

			size += obj->gtt_space->size;

			++count;

		   dev_priv->gtt.total,

		   dev_priv->gtt.mappable_end - dev_priv->gtt.start);

	seq_printf(m, "\n");

	list_for_each_entry_reverse(file, &dev->filelist, lhead) {

		struct file_stats stats;

		memset(&stats, 0, sizeof(stats));

		idr_for_each(&file->object_idr, per_file_stats, &stats);

		seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",

			   get_pid_task(file->pid, PIDTYPE_PID)->comm,

			   stats.count,

			   stats.total,

			   stats.active,

			   stats.inactive,

			   stats.unbound);

	}

	mutex_unlock(&dev->struct_mutex);

	return 0;

		return ret;

	total_obj_size = total_gtt_size = count = 0;

	list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {

	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {

		if (list == PINNED_LIST && obj->pin_count == 0)

			continue;

	}

	if (val & DROP_UNBOUND) {

		list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)

		list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,

					 global_list)

			if (obj->pages_pin_count == 0) {

				ret = i915_gem_object_put_pages(obj);

				if (ret)

		value = 1;

		break;

	default:

		DRM_DEBUG_DRIVER("Unknown parameter %d\n",

				 param->param);

		DRM_DEBUG("Unknown parameter %d\n", param->param);

		return -EINVAL;

	}

	/* Start out suspended */

	dev_priv->mm.suspended = 1;

	if (HAS_POWER_WELL(dev))

		i915_init_power_well(dev);

	if (drm_core_check_feature(dev, DRIVER_MODESET)) {

		ret = i915_load_modeset_init(dev);

		if (ret < 0) {

	intel_gpu_ips_teardown();

	if (HAS_POWER_WELL(dev))

		i915_remove_power_well(dev);

	i915_teardown_sysfs(dev);

	if (dev_priv->mm.inactive_shrinker.shrink)

	struct drm_i915_file_private *file_priv;

	DRM_DEBUG_DRIVER("\n");

	file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);

	file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);

	if (!file_priv)

		return -ENOMEM;

	 */

	if (INTEL_INFO(dev)->num_pipes == 0) {

		dev_priv->pch_type = PCH_NOP;

		dev_priv->num_pch_pll = 0;

		return;

	}

			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {

				dev_priv->pch_type = PCH_IBX;

				dev_priv->num_pch_pll = 2;

				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");

				WARN_ON(!IS_GEN5(dev));

			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {

				dev_priv->pch_type = PCH_CPT;

				dev_priv->num_pch_pll = 2;

				DRM_DEBUG_KMS("Found CougarPoint PCH\n");

				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));

			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {

				/* PantherPoint is CPT compatible */

				dev_priv->pch_type = PCH_CPT;

				dev_priv->num_pch_pll = 2;

				DRM_DEBUG_KMS("Found PatherPoint PCH\n");

				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));

			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {

				dev_priv->pch_type = PCH_LPT;

				dev_priv->num_pch_pll = 0;

				DRM_DEBUG_KMS("Found LynxPoint PCH\n");

				WARN_ON(!IS_HASWELL(dev));

				WARN_ON(IS_ULT(dev));

			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {

				dev_priv->pch_type = PCH_LPT;

				dev_priv->num_pch_pll = 0;

				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");

				WARN_ON(!IS_HASWELL(dev));

				WARN_ON(!IS_ULT(dev));

			}

			BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);

		}

		pci_dev_put(pch);

	}

	intel_opregion_fini(dev);

	console_lock();

	intel_fbdev_set_suspend(dev, 1);

	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);

	console_unlock();

	return 0;

	struct drm_device *dev = dev_priv->dev;

	console_lock();

	intel_fbdev_set_suspend(dev, 0);

	intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);

	console_unlock();

}

	 * path of resume if possible.

	 */

	if (console_trylock()) {

		intel_fbdev_set_suspend(dev, 0);

		intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);

		console_unlock();

	} else {

		schedule_work(&dev_priv->console_resume_work);

	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \

		if ((intel_encoder)->base.crtc == (__crtc))

struct intel_pch_pll {

struct drm_i915_private;

enum intel_dpll_id {

	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */

	/* real shared dpll ids must be >= 0 */

	DPLL_ID_PCH_PLL_A,

	DPLL_ID_PCH_PLL_B,

};

#define I915_NUM_PLLS 2

struct intel_dpll_hw_state {

	uint32_t dpll;

	uint32_t fp0;

	uint32_t fp1;

};

struct intel_shared_dpll {

	int refcount; /* count of number of CRTCs sharing this PLL */

	int active; /* count of number of active CRTCs (i.e. DPMS on) */

	bool on; /* is the PLL actually active? Disabled during modeset */

	int pll_reg;

	int fp0_reg;

	int fp1_reg;

	const char *name;

	/* should match the index in the dev_priv->shared_dplls array */

	enum intel_dpll_id id;

	struct intel_dpll_hw_state hw_state;

	void (*enable)(struct drm_i915_private *dev_priv,

		       struct intel_shared_dpll *pll);

	void (*disable)(struct drm_i915_private *dev_priv,

			struct intel_shared_dpll *pll);

	bool (*get_hw_state)(struct drm_i915_private *dev_priv,

			     struct intel_shared_dpll *pll,

			     struct intel_dpll_hw_state *hw_state);

};

#define I915_NUM_PLLS 2

/* Used by dp and fdi links */

struct intel_link_m_n {

struct opregion_acpi;

struct opregion_swsci;

struct opregion_asle;

struct drm_i915_private;

struct intel_opregion {

	struct opregion_header __iomem *header;

struct intel_crtc_config;

struct intel_crtc;

struct intel_limit;

struct dpll;

struct drm_i915_display_funcs {

	bool (*fbc_enabled)(struct drm_device *dev);

	void (*disable_fbc)(struct drm_device *dev);

	int (*get_display_clock_speed)(struct drm_device *dev);

	int (*get_fifo_size)(struct drm_device *dev, int plane);

	/**

	 * find_dpll() - Find the best values for the PLL

	 * @limit: limits for the PLL

	 * @crtc: current CRTC

	 * @target: target frequency in kHz

	 * @refclk: reference clock frequency in kHz

	 * @match_clock: if provided, @best_clock P divider must

	 *               match the P divider from @match_clock

	 *               used for LVDS downclocking

	 * @best_clock: best PLL values found

	 *

	 * Returns true on success, false on failure.

	 */

	bool (*find_dpll)(const struct intel_limit *limit,

			  struct drm_crtc *crtc,

			  int target, int refclk,

			  struct dpll *match_clock,

			  struct dpll *best_clock);

	void (*update_wm)(struct drm_device *dev);

	void (*update_sprite_wm)(struct drm_device *dev, int pipe,

				 uint32_t sprite_width, int pixel_size,

	void (*cleanup)(struct i915_hw_ppgtt *ppgtt);

};

struct i915_ctx_hang_stats {

	/* This context had batch pending when hang was declared */

	unsigned batch_pending;

	/* This context had batch active when hang was declared */

	unsigned batch_active;

};

/* This must match up with the value previously used for execbuf2.rsvd1. */

#define DEFAULT_CONTEXT_ID 0

	struct drm_i915_file_private *file_priv;

	struct intel_ring_buffer *ring;

	struct drm_i915_gem_object *obj;

	struct i915_ctx_hang_stats hang_stats;

};

enum no_fbc_reason {

	struct drm_i915_gem_object *renderctx;

};

/* Power well structure for haswell */

struct i915_power_well {

	struct drm_device *device;

	spinlock_t lock;

	/* power well enable/disable usage count */

	int count;

	int i915_request;

};

struct i915_dri1_state {

	unsigned allow_batchbuffer : 1;

	u32 __iomem *gfx_hws_cpu_addr;

#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */

#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)

	struct timer_list hangcheck_timer;

	int hangcheck_count;

	/* For reset and error_state handling. */

	spinlock_t lock;

	u32 hpd_event_bits;

	struct timer_list hotplug_reenable_timer;

	int num_pch_pll;

	int num_plane;

	unsigned long cfb_size;

	struct drm_crtc *pipe_to_crtc_mapping[3];

	wait_queue_head_t pending_flip_queue;

	struct intel_pch_pll pch_plls[I915_NUM_PLLS];

	int num_shared_dpll;

	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];

	struct intel_ddi_plls ddi_plls;

	/* Reclocking support */

	 * mchdev_lock in intel_pm.c */

	struct intel_ilk_power_mgmt ips;

	/* Haswell power well */

	struct i915_power_well power_well;

	enum no_fbc_reason no_fbc_reason;

	struct drm_mm_node *compressed_fb;

	struct drm_mm_node *gtt_space;

	/** Stolen memory for this object, instead of being backed by shmem. */

	struct drm_mm_node *stolen;

	struct list_head gtt_list;

	struct list_head global_list;

	/** This object's place on the active/inactive lists */

	struct list_head ring_list;

	/** GEM sequence number associated with this request. */

	uint32_t seqno;

	/** Postion in the ringbuffer of the end of the request */

	/** Position in the ringbuffer of the start of the request */

	u32 head;

	/** Position in the ringbuffer of the end of the request */

	u32 tail;

	/** Context related to this request */

	struct i915_hw_context *ctx;

	/** Batch buffer related to this request if any */

	struct drm_i915_gem_object *batch_obj;

	/** Time at which this request was emitted, in jiffies. */

	unsigned long emitted_jiffies;

		struct list_head request_list;

	} mm;

	struct idr context_idr;

	struct i915_ctx_hang_stats hang_stats;

};

#define INTEL_INFO(dev)	(((struct drm_i915_private *) (dev)->dev_private)->info)

{

	if (obj->fence_reg != I915_FENCE_REG_NONE) {

		struct drm_i915_private *dev_priv = obj->base.dev->dev_private;

		WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);

		dev_priv->fence_regs[obj->fence_reg].pin_count--;

	}

}

void i915_gem_cleanup_ringbuffer(struct drm_device *dev);

int __must_check i915_gpu_idle(struct drm_device *dev);

int __must_check i915_gem_idle(struct drm_device *dev);

int i915_add_request(struct intel_ring_buffer *ring,

int __i915_add_request(struct intel_ring_buffer *ring,

		       struct drm_file *file,

		       struct drm_i915_gem_object *batch_obj,

		       u32 *seqno);

#define i915_add_request(ring, seqno) \

	__i915_add_request(ring, NULL, NULL, seqno)

int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,

				 uint32_t seqno);

int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);

	kref_put(&ctx->ref, i915_gem_context_free);

}

struct i915_ctx_hang_stats * __must_check

i915_gem_context_get_hang_stats(struct intel_ring_buffer *ring,

				struct drm_file *file,

				u32 id);

int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,

				  struct drm_file *file);

int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,

	pinned = 0;

	mutex_lock(&dev->struct_mutex);

	list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)

	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)

		if (obj->pin_count)

			pinned += obj->gtt_space->size;

	mutex_unlock(&dev->struct_mutex);

	ret = 0;

	if (seqno == ring->outstanding_lazy_request)

		ret = i915_add_request(ring, NULL, NULL);

		ret = i915_add_request(ring, NULL);

	return ret;

}

	/* ->put_pages might need to allocate memory for the bit17 swizzle

	 * array, hence protect them from being reaped by removing them from gtt

	 * lists early. */

	list_del(&obj->gtt_list);

	list_del(&obj->global_list);

	ops->put_pages(obj);

	obj->pages = NULL;

	list_for_each_entry_safe(obj, next,

				 &dev_priv->mm.unbound_list,

				 gtt_list) {

				 global_list) {

		if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&

		    i915_gem_object_put_pages(obj) == 0) {

			count += obj->base.size >> PAGE_SHIFT;

	i915_gem_evict_everything(dev_priv->dev);

	list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)

	list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,

				 global_list)

		i915_gem_object_put_pages(obj);

}

	if (ret)

		return ret;

	list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);

	list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);

	return 0;

}

	return 0;

}

int

i915_add_request(struct intel_ring_buffer *ring,

int __i915_add_request(struct intel_ring_buffer *ring,

		       struct drm_file *file,

		       struct drm_i915_gem_object *obj,

		       u32 *out_seqno)

{

	drm_i915_private_t *dev_priv = ring->dev->dev_private;

	struct drm_i915_gem_request *request;

	u32 request_ring_position;

	u32 request_ring_position, request_start;

	int was_empty;

	int ret;

	request_start = intel_ring_get_tail(ring);

	/*

	 * Emit any outstanding flushes - execbuf can fail to emit the flush

	 * after having emitted the batchbuffer command. Hence we need to fix

	request->seqno = intel_ring_get_seqno(ring);

	request->ring = ring;

	request->head = request_start;

	request->tail = request_ring_position;

	request->ctx = ring->last_context;

	request->batch_obj = obj;

	/* Whilst this request exists, batch_obj will be on the

	 * active_list, and so will hold the active reference. Only when this

	 * request is retired will the the batch_obj be moved onto the

	 * inactive_list and lose its active reference. Hence we do not need

	 * to explicitly hold another reference here.

	 */

	if (request->ctx)

		i915_gem_context_reference(request->ctx);

	spin_unlock(&file_priv->mm.lock);

}

static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj)

{

	if (acthd >= obj->gtt_offset &&

	    acthd < obj->gtt_offset + obj->base.size)

		return true;

	return false;

}

static bool i915_head_inside_request(const u32 acthd_unmasked,

				     const u32 request_start,

				     const u32 request_end)

{

	const u32 acthd = acthd_unmasked & HEAD_ADDR;

	if (request_start < request_end) {

		if (acthd >= request_start && acthd < request_end)

			return true;

	} else if (request_start > request_end) {

		if (acthd >= request_start || acthd < request_end)

			return true;

	}

	return false;

}

static bool i915_request_guilty(struct drm_i915_gem_request *request,

				const u32 acthd, bool *inside)

{

	/* There is a possibility that unmasked head address

	 * pointing inside the ring, matches the batch_obj address range.

	 * However this is extremely unlikely.

	 */

	if (request->batch_obj) {

		if (i915_head_inside_object(acthd, request->batch_obj)) {

			*inside = true;

			return true;

		}

	}

	if (i915_head_inside_request(acthd, request->head, request->tail)) {

		*inside = false;

		return true;

	}

	return false;

}

static void i915_set_reset_status(struct intel_ring_buffer *ring,

				  struct drm_i915_gem_request *request,

				  u32 acthd)

{

	struct i915_ctx_hang_stats *hs = NULL;

	bool inside, guilty;

	/* Innocent until proven guilty */

	guilty = false;

	if (ring->hangcheck.action != wait &&

	    i915_request_guilty(request, acthd, &inside)) {

		DRM_ERROR("%s hung %s bo (0x%x ctx %d) at 0x%x\n",

			  ring->name,

			  inside ? "inside" : "flushing",

			  request->batch_obj ?

			  request->batch_obj->gtt_offset : 0,

			  request->ctx ? request->ctx->id : 0,

			  acthd);

		guilty = true;

	}

	/* If contexts are disabled or this is the default context, use

	 * file_priv->reset_state

	 */

	if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)

		hs = &request->ctx->hang_stats;

	else if (request->file_priv)

		hs = &request->file_priv->hang_stats;

	if (hs) {

		if (guilty)

			hs->batch_active++;

		else

			hs->batch_pending++;