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Commit 27b67278 authored by Lucas Stach's avatar Lucas Stach
Browse files

drm/etnaviv: rework MMU handling 



This reworks the MMU handling to make it possible to have multiple MMU contexts.
A context is basically one instance of GPU page tables. Currently we have one
set of page tables per GPU, which isn't all that clever, as it has the
following two consequences:

1. All GPU clients (aka processes) are sharing the same pagetables, which means
there is no isolation between clients, but only between GPU assigned memory
spaces and the rest of the system. Better than nothing, but also not great.

2. Clients operating on the same set of buffers with different etnaviv GPU
cores, e.g. a workload using both the 2D and 3D GPU, need to map the used
buffers into the pagetable sets of each used GPU.

This patch reworks all the MMU handling to introduce the abstraction of the
MMU context. A context can be shared across different GPU cores, as long as
they have compatible MMU implementations, which is the case for all systems
with Vivante GPUs seen in the wild.

As MMUv1 is not able to change pagetables on the fly, without a
"stop the world" operation, which stops GPU, changes pagetables via CPU
interaction, restarts GPU, the implementation introduces a shared context on
MMUv1, which is returned whenever there is a request for a new context.

This patch assigns a MMU context to each GPU, so on MMUv2 systems there is
still one set of pagetables per GPU, but due to the shared context MMUv1
systems see a change in behavior as now a single pagetable set is used
across all GPU cores.

Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Reviewed-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: default avatarGuido Günther <agx@sigxcpu.org>
parent 4900dda9

drivers/gpu/drm/etnaviv/etnaviv_buffer.c

+5 −5
Original line number Diff line number Diff line
@@ -207,7 +207,7 @@ u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe 
	return buffer->user_size / 8;

}



u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu)

u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id)

{

	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
@@ -216,7 +216,7 @@ u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu) 
	buffer->user_size = 0;



	CMD_LOAD_STATE(buffer, VIVS_MMUv2_PTA_CONFIG,

		       VIVS_MMUv2_PTA_CONFIG_INDEX(0));

		       VIVS_MMUv2_PTA_CONFIG_INDEX(id));



	CMD_END(buffer);
@@ -315,7 +315,7 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state, 
	u32 return_target, return_dwords;

	u32 link_target, link_dwords;

	bool switch_context = gpu->exec_state != exec_state;

	unsigned int new_flush_seq = READ_ONCE(gpu->mmu->flush_seq);

	unsigned int new_flush_seq = READ_ONCE(gpu->mmu_context->flush_seq);

	bool need_flush = gpu->flush_seq != new_flush_seq;



	lockdep_assert_held(&gpu->lock);
@@ -339,7 +339,7 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state, 


		/* flush command */

		if (need_flush) {

			if (gpu->mmu->version == ETNAVIV_IOMMU_V1)

			if (gpu->mmu_context->global->version == ETNAVIV_IOMMU_V1)

				extra_dwords += 1;

			else

				extra_dwords += 3;
@@ -353,7 +353,7 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state, 


		if (need_flush) {

			/* Add the MMU flush */

			if (gpu->mmu->version == ETNAVIV_IOMMU_V1) {

			if (gpu->mmu_context->global->version == ETNAVIV_IOMMU_V1) {

				CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_MMU,

					       VIVS_GL_FLUSH_MMU_FLUSH_FEMMU |

					       VIVS_GL_FLUSH_MMU_FLUSH_UNK1 |

drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.c

+4 −4
Original line number Diff line number Diff line
@@ -60,18 +60,18 @@ etnaviv_cmdbuf_suballoc_new(struct device *dev) 
}



int etnaviv_cmdbuf_suballoc_map(struct etnaviv_cmdbuf_suballoc *suballoc,

				struct etnaviv_iommu *mmu,

				struct etnaviv_iommu_context *context,

				struct etnaviv_vram_mapping *mapping,

				u32 memory_base)

{

	return etnaviv_iommu_get_suballoc_va(mmu, mapping, memory_base,

	return etnaviv_iommu_get_suballoc_va(context, mapping, memory_base,

					     suballoc->paddr, SUBALLOC_SIZE);

}



void etnaviv_cmdbuf_suballoc_unmap(struct etnaviv_iommu *mmu,

void etnaviv_cmdbuf_suballoc_unmap(struct etnaviv_iommu_context *context,

				   struct etnaviv_vram_mapping *mapping)

{

	etnaviv_iommu_put_suballoc_va(mmu, mapping);

	etnaviv_iommu_put_suballoc_va(context, mapping);

}



void etnaviv_cmdbuf_suballoc_destroy(struct etnaviv_cmdbuf_suballoc *suballoc)

drivers/gpu/drm/etnaviv/etnaviv_cmdbuf.h

+3 −3
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ 
#include <linux/types.h>



struct device;

struct etnaviv_iommu;

struct etnaviv_iommu_context;

struct etnaviv_vram_mapping;

struct etnaviv_cmdbuf_suballoc;

struct etnaviv_perfmon_request;
@@ -28,10 +28,10 @@ struct etnaviv_cmdbuf_suballoc * 
etnaviv_cmdbuf_suballoc_new(struct device *dev);

void etnaviv_cmdbuf_suballoc_destroy(struct etnaviv_cmdbuf_suballoc *suballoc);

int etnaviv_cmdbuf_suballoc_map(struct etnaviv_cmdbuf_suballoc *suballoc,

				struct etnaviv_iommu *mmu,

				struct etnaviv_iommu_context *context,

				struct etnaviv_vram_mapping *mapping,

				u32 memory_base);

void etnaviv_cmdbuf_suballoc_unmap(struct etnaviv_iommu *mmu,

void etnaviv_cmdbuf_suballoc_unmap(struct etnaviv_iommu_context *context,

				   struct etnaviv_vram_mapping *mapping);

drivers/gpu/drm/etnaviv/etnaviv_drv.c

+3 −3
Original line number Diff line number Diff line
@@ -119,9 +119,9 @@ static int etnaviv_mmu_show(struct etnaviv_gpu *gpu, struct seq_file *m) 


	seq_printf(m, "Active Objects (%s):\n", dev_name(gpu->dev));



	mutex_lock(&gpu->mmu->lock);

	drm_mm_print(&gpu->mmu->mm, &p);

	mutex_unlock(&gpu->mmu->lock);

	mutex_lock(&gpu->mmu_context->lock);

	drm_mm_print(&gpu->mmu_context->mm, &p);

	mutex_unlock(&gpu->mmu_context->lock);



	return 0;

}

drivers/gpu/drm/etnaviv/etnaviv_drv.h

+3 −1
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ struct etnaviv_gpu; 
struct etnaviv_mmu;

struct etnaviv_gem_object;

struct etnaviv_gem_submit;

struct etnaviv_iommu_global;



struct etnaviv_file_private {

	/*
@@ -37,6 +38,7 @@ struct etnaviv_drm_private { 
	struct etnaviv_gpu *gpu[ETNA_MAX_PIPES];



	struct etnaviv_cmdbuf_suballoc *cmdbuf_suballoc;

	struct etnaviv_iommu_global *mmu_global;



	/* list of GEM objects: */

	struct mutex gem_lock;
@@ -69,7 +71,7 @@ int etnaviv_gem_new_userptr(struct drm_device *dev, struct drm_file *file, 
	uintptr_t ptr, u32 size, u32 flags, u32 *handle);

u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu);

u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr);

u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu);

u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id);

void etnaviv_buffer_end(struct etnaviv_gpu *gpu);

void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event);

void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,