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Commit 273f2d7e authored by Kevin Cernekee's avatar Kevin Cernekee Committed by Ralf Baechle
Browse files

MIPS: Install handlers for software IRQs 



BMIPS4350/4380/5000 CMT/SMT all use SW INT0/INT1 for inter-thread
signaling.

Signed-off-by: default avatarKevin Cernekee <cernekee@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1709/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 565b60de

arch/mips/kernel/irq_cpu.c

+6 −8
Original line number Original line Diff line number Diff line
@@ -103,13 +103,11 @@ void __init mips_cpu_irq_init(void) 
	clear_c0_status(ST0_IM);

	clear_c0_status(ST0_IM);

	clear_c0_cause(CAUSEF_IP);

	clear_c0_cause(CAUSEF_IP);





	/*

	/* Software interrupts are used for MT/CMT IPI */

	 * Only MT is using the software interrupts currently, so we just

	 * leave them uninitialized for other processors.

	 */

	if (cpu_has_mipsmt)

	for (i = irq_base; i < irq_base + 2; i++)

	for (i = irq_base; i < irq_base + 2; i++)

			irq_set_chip_and_handler(i, &mips_mt_cpu_irq_controller,

		irq_set_chip_and_handler(i, cpu_has_mipsmt ?

					 &mips_mt_cpu_irq_controller :

					 &mips_cpu_irq_controller,

					 handle_percpu_irq);

					 handle_percpu_irq);





	for (i = irq_base + 2; i < irq_base + 8; i++)

	for (i = irq_base + 2; i < irq_base + 8; i++)