disp: pll: Fix cfg1 value when pclk_src_mux parent is updated

Currently, PLL_CFG1(1:0) register is updated with cached values
in dsi_pll_enable. This can create issue when UEFI and kernel
cfg1 programming is not same. To fix it, return cached value
of cfg1 when its read in pclk_mux_read, so that pclk_mux_write
is called and cached value is updated. This fix is for 10nm pll.

Change-Id: I8465cb9027a1639f3cdeb02274513ac680f84632
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>