Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 272f660e authored by Ritesh Kumar's avatar Ritesh Kumar Committed by Gerrit - the friendly Code Review server
Browse files

disp: pll: Fix cfg1 value when pclk_src_mux parent is updated 



Currently, PLL_CFG1(1:0) register is updated with cached values
in dsi_pll_enable. This can create issue when UEFI and kernel
cfg1 programming is not same. To fix it, return cached value
of cfg1 when its read in pclk_mux_read, so that pclk_mux_write
is called and cached value is updated. This fix is for 10nm pll.

Change-Id: I8465cb9027a1639f3cdeb02274513ac680f84632
Signed-off-by: default avatarRitesh Kumar <riteshk@codeaurora.org>
parent 043cd065

msm/dsi/dsi_pll_10nm.c

+7 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.

 */



#define pr_fmt(fmt)	"%s: " fmt, __func__
@@ -282,6 +282,12 @@ static inline int pclk_mux_read_sel(void *context, unsigned int reg, 
	int rc = 0;

	struct dsi_pll_resource *rsc = context;



	/* Return cached cfg1 as its updated with cached cfg1 in pll_enable */

	if (!rsc->handoff_resources) {

		*val = (rsc->cached_cfg1) & 0x3;

		return rc;

	}



	*val = (DSI_PLL_REG_R(rsc->phy_base, reg) & 0x3);



	return rc;