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Commit 271dbe10 authored by Vatsal Bucha's avatar Vatsal Bucha Committed by Gerrit - the friendly Code Review server
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ASoC: Remove glitch during amic record 



Glitch is coming sometimes during amic record.
Correct sequence to resolve the glitch.

Change-Id: I3c062632229826f6fe32e2f1ea9e07381c21d902
Signed-off-by: default avatarVatsal Bucha <vbucha@codeaurora.org>
parent f34687bd

asoc/codecs/bolero/tx-macro.c

+24 −15
Original line number Diff line number Diff line
@@ -902,13 +902,14 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 
	case SND_SOC_DAPM_POST_PMU:

		snd_soc_component_update_bits(component,

			tx_vol_ctl_reg, 0x20, 0x20);

		if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)) {

			snd_soc_component_update_bits(component,

				hpf_gate_reg, 0x01, 0x00);

			/*

		 	 * Minimum 1 clk cycle delay is required as per HW spec

		 	 */

			usleep_range(1000, 1010);



		}

		hpf_cut_off_freq = (

			snd_soc_component_read32(component, dec_cfg_reg) &

				TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
@@ -937,15 +938,17 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 
				&tx_priv->tx_hpf_work[decimator].dwork,

				msecs_to_jiffies(hpf_delay));

			snd_soc_component_update_bits(component,

					hpf_gate_reg, 0x03, 0x03);

					hpf_gate_reg, 0x03, 0x02);

			if (!(is_amic_enabled(component, decimator)

				< BOLERO_ADC_MAX))

				snd_soc_component_update_bits(component,

					hpf_gate_reg, 0x03, 0x00);

			/*

			 * Minimum 1 clk cycle delay is required as per HW spec

			 */

			usleep_range(1000, 1010);

			snd_soc_component_update_bits(component,

					hpf_gate_reg, 0x02, 0x00);

			snd_soc_component_update_bits(component,

					hpf_gate_reg, 0x01, 0x01);

					hpf_gate_reg, 0x03, 0x01);

			/*

			 * 6ms delay is required as per HW spec

			 */
@@ -1012,9 +1015,15 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 
						component, dec_cfg_reg,

						TX_HPF_CUT_OFF_FREQ_MASK,

						hpf_cut_off_freq << 5);

				if (is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)

					snd_soc_component_update_bits(component,

							hpf_gate_reg,

						0x02, 0x02);

							0x03, 0x02);

				else

					snd_soc_component_update_bits(component,

							hpf_gate_reg,

							0x03, 0x03);



				/*

				 * Minimum 1 clk cycle delay is required

				 * as per HW spec
@@ -1022,7 +1031,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 
				usleep_range(1000, 1010);

				snd_soc_component_update_bits(component,

						hpf_gate_reg,

						0x02, 0x00);

						0x03, 0x01);

			}

		}

		cancel_delayed_work_sync(

asoc/codecs/bolero/va-macro.c

+21 −13
Original line number Diff line number Diff line
@@ -1074,13 +1074,14 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 
		/* Enable TX CLK */

		snd_soc_component_update_bits(component,

				tx_vol_ctl_reg, 0x20, 0x20);

		if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)) {

			snd_soc_component_update_bits(component,

				hpf_gate_reg, 0x01, 0x00);

			/*

		 	 * Minimum 1 clk cycle delay is required as per HW spec

		 	 */

			usleep_range(1000, 1010);



		}

		hpf_cut_off_freq = (snd_soc_component_read32(

					component, dec_cfg_reg) &

				   TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
@@ -1099,15 +1100,16 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 
				va_tx_unmute_delay = unmute_delay;

		}

		snd_soc_component_update_bits(component,

				hpf_gate_reg, 0x03, 0x03);

				hpf_gate_reg, 0x03, 0x02);

		if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX))

			snd_soc_component_update_bits(component,

				hpf_gate_reg, 0x03, 0x00);

		/*

		 * Minimum 1 clk cycle delay is required as per HW spec

		 */

		usleep_range(1000, 1010);

		snd_soc_component_update_bits(component,

			hpf_gate_reg, 0x02, 0x00);

		snd_soc_component_update_bits(component,

			hpf_gate_reg, 0x01, 0x01);

			hpf_gate_reg, 0x03, 0x01);

		/*

		 * 6ms delay is required as per HW spec

		 */
@@ -1163,9 +1165,15 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 
						dec_cfg_reg,

						TX_HPF_CUT_OFF_FREQ_MASK,

						hpf_cut_off_freq << 5);

				if (is_amic_enabled(component, decimator) <

					BOLERO_ADC_MAX)

					snd_soc_component_update_bits(component,

						hpf_gate_reg,

						0x02, 0x02);

						0x03, 0x02);

				else

					snd_soc_component_update_bits(component,

						hpf_gate_reg,

						0x03, 0x03);

				/*

				 * Minimum 1 clk cycle delay is required

				 * as per HW spec
@@ -1173,7 +1181,7 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 
				usleep_range(1000, 1010);

				snd_soc_component_update_bits(component,

						hpf_gate_reg,

						0x02, 0x00);

						0x03, 0x01);

			}

		}

		cancel_delayed_work_sync(